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2022-06-29 - 15:07

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 03, 2022 02:52:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1406399236232,2cyclictest0-21swapper/1322:29:195
1406399236232,2cyclictest0-21swapper/1322:29:195
1405899221209,5cyclictest4303-21CPU2
1405899221209,5cyclictest4303-21CPU2
1405899213199,11cyclictest35477-21cp21:35:162
1405899213199,11cyclictest35477-21cp21:35:162
1405899212190,13cyclictest0-21swapper/1000:12:122
1405899212190,13cyclictest0-21swapper/1000:12:122
1405899211190,11cyclictest0-21swapper/1000:01:432
1405899211190,11cyclictest0-21swapper/1000:01:432
1407299210206,2cyclictest0-21swapper/1922:30:1711
1407299210206,2cyclictest0-21swapper/1922:30:1711
1407299208204,2cyclictest0-21swapper/1923:05:3711
1407299208204,2cyclictest0-21swapper/1923:05:3711
1407299208204,2cyclictest0-21swapper/1923:05:3711
1405899207197,5cyclictest4299-21CPU2
1405899206193,6cyclictest4300-21CPU2
1405899206193,6cyclictest4300-21CPU2
1405899204197,5cyclictest0-21swapper/1023:13:162
1405899204197,5cyclictest0-21swapper/1023:13:162
1405899204185,11cyclictest0-21swapper/1021:56:522
1405899204185,11cyclictest0-21swapper/1021:56:522
1405899204185,11cyclictest0-21swapper/1021:56:522
1405899203194,6cyclictest0-21swapper/1023:32:042
1405899203194,6cyclictest0-21swapper/1023:32:042
1405899203192,6cyclictest4298-21CPU2
1405899203192,6cyclictest4298-21CPU2
1405899203192,6cyclictest19424-21CPU2
1405899203192,6cyclictest19424-21CPU2
14074992021,158cyclictest0-21swapper/2023:36:5213
14074992021,158cyclictest0-21swapper/2023:36:5213
1405899202194,5cyclictest18709-21rs:main2
1405899202194,5cyclictest18709-21rs:main2
1405899202192,7cyclictest0-21swapper/1022:45:512
1405899202192,7cyclictest0-21swapper/1022:45:512
1405899202190,9cyclictest12534-21polkitd21:26:302
1405899202190,9cyclictest12534-21polkitd21:26:302
1405899201194,5cyclictest0-21swapper/1000:37:112
1405899201194,5cyclictest0-21swapper/1000:37:112
1405899201194,5cyclictest0-21swapper/1000:37:112
1405899201183,16cyclictest0-21swapper/1022:43:302
1405899201183,16cyclictest0-21swapper/1022:43:302
1405899201183,16cyclictest0-21swapper/1022:43:302
14075992000,166cyclictest34319-21sshd22:29:5314
14075992000,166cyclictest34319-21sshd22:29:5314
14074992001,136cyclictest0-21swapper/2019:40:1513
1405899200193,5cyclictest0-21swapper/1022:53:442
1405899200193,5cyclictest0-21swapper/1022:53:442
1405899200193,5cyclictest0-21swapper/1022:53:442
1405899200191,4cyclictest4301-21CPU2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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