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2023-01-28 - 11:12

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 28, 2023 02:55:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3731799265259,3cyclictest0-21swapper/819:15:1638
3731799265259,3cyclictest0-21swapper/819:15:1638
3732699247244,1cyclictest0-21swapper/1400:25:256
3732699247244,1cyclictest0-21swapper/1400:25:256
3734299240236,2cyclictest0-21swapper/2719:15:1520
3734299240236,2cyclictest0-21swapper/2719:15:1520
3734599232227,3cyclictest0-21swapper/2920:35:2322
3734599232227,3cyclictest0-21swapper/2920:35:2322
3734599231227,2cyclictest0-21swapper/2919:15:1722
3734599231227,2cyclictest0-21swapper/2919:15:1722
3734599228223,2cyclictest10004-21sshd22:03:3522
3734599228223,2cyclictest10004-21sshd22:03:3522
3735599227223,2cyclictest0-21swapper/3521:30:3329
3735599227223,2cyclictest0-21swapper/3521:30:3329
3734599218211,3cyclictest0-21swapper/2919:55:1522
3734599218211,3cyclictest0-21swapper/2919:55:1522
3733099218211,3cyclictest25029-21CPU9
3733099218211,3cyclictest25029-21CPU9
3733099218211,3cyclictest25029-21CPU9
3732699216209,3cyclictest25032-21CPU6
3732699216209,3cyclictest25032-21CPU6
3733699213209,2cyclictest0-21swapper/2119:15:2514
3733699213209,2cyclictest0-21swapper/2119:15:2514
3730799209198,3cyclictest251rcuc/121:53:461
3730799209198,3cyclictest251rcuc/121:53:461
3734799208204,2cyclictest0-21swapper/3022:50:3224
3734799208204,2cyclictest0-21swapper/3022:50:3224
3734799208204,2cyclictest0-21swapper/3022:50:3224
3733099207204,1cyclictest0-21swapper/1700:25:019
3733099207204,1cyclictest0-21swapper/1700:25:019
3734199205201,2cyclictest0-21swapper/2619:15:2519
3734199205201,2cyclictest0-21swapper/2619:15:2519
2093022050,2sleep340-21swapper/3419:05:1428
2093022050,2sleep340-21swapper/3419:05:1428
3735799204199,2cyclictest0-21swapper/3600:35:2430
3735799204199,2cyclictest0-21swapper/3600:35:2430
3732699203197,3cyclictest0-21swapper/1400:24:296
3732699203197,3cyclictest0-21swapper/1400:24:296
3731799203198,2cyclictest0-21swapper/821:22:4738
3731799203198,2cyclictest0-21swapper/821:22:4738
3733899202198,2cyclictest23787-21sshd00:07:4116
3733899202198,2cyclictest23787-21sshd00:07:4116
3730999201198,1cyclictest0-21swapper/219:15:1212
3730999201198,1cyclictest0-21swapper/219:15:1112
3735599200197,1cyclictest0-21swapper/3519:50:1229
3735599200197,1cyclictest0-21swapper/3519:50:1229
373409920012,183cyclictest0-21swapper/2519:15:2418
373409920012,183cyclictest0-21swapper/2519:15:2418
3734199199194,3cyclictest0-21swapper/2619:13:5619
3734199199194,3cyclictest0-21swapper/2619:13:5619
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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