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2024-04-25 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Thu Apr 25, 2024 13:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3278599219187,28cyclictest0-21swapper/212:37:3612
3278599219187,28cyclictest0-21swapper/212:37:3612
3278599219187,28cyclictest0-21swapper/212:37:3612
3281099205191,12cyclictest1992-21nfsd10:34:5120
3281099205191,12cyclictest1992-21nfsd10:34:5120
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799204192,10cyclictest0-21swapper/3411:22:5528
3281799199178,11cyclictest0-21swapper/3410:06:1028
3281799199178,11cyclictest0-21swapper/3410:06:1028
3279399197153,34cyclictest171rcu_preempt10:45:112
3279399197153,34cyclictest171rcu_preempt10:45:112
3279399197153,34cyclictest171rcu_preempt10:45:102
3281499196183,7cyclictest171rcu_preempt10:27:1625
3281499196183,7cyclictest171rcu_preempt10:27:1625
3281499196183,7cyclictest171rcu_preempt10:27:1625
3279699194156,33cyclictest15983-21CPU5
3279699194156,33cyclictest15983-21CPU5
3280599193183,5cyclictest0-21swapper/2209:40:1015
3280599193183,5cyclictest0-21swapper/2209:40:1015
3280499192131,38cyclictest0-21swapper/2108:20:5214
3280499192131,38cyclictest0-21swapper/2108:20:5214
328019919210,81cyclictest0-21swapper/1812:10:1910
328019919210,81cyclictest0-21swapper/1812:10:1910
32801991919,159cyclictest4910-21CPU10
32801991919,159cyclictest4910-21CPU10
32801991919,159cyclictest4910-21CPU10
3280499190146,20cyclictest0-21swapper/2107:17:1114
3280499190146,20cyclictest0-21swapper/2107:17:1114
3280499189144,30cyclictest0-21swapper/2108:57:3714
3279699189151,30cyclictest0-21swapper/1312:09:515
3279699189151,30cyclictest0-21swapper/1312:09:515
3279699189151,30cyclictest0-21swapper/1312:09:515
3279699189128,24cyclictest0-21swapper/1311:58:005
3279699189128,24cyclictest0-21swapper/1311:58:005
3279699189128,24cyclictest0-21swapper/1311:57:595
3280499187147,24cyclictest0-21swapper/2111:18:1214
3280499187147,24cyclictest0-21swapper/2111:18:1214
3281799186155,17cyclictest0-21swapper/3408:45:0228
3281799186155,17cyclictest0-21swapper/3408:45:0228
3281499186169,9cyclictest171rcu_preempt10:19:2125
3281499186169,9cyclictest171rcu_preempt10:19:2125
3281499186169,9cyclictest171rcu_preempt10:19:2125
3281099186177,7cyclictest0-21swapper/2709:13:4120
3281099186177,7cyclictest0-21swapper/2709:13:4120
3281099186177,7cyclictest0-21swapper/2709:13:4120
3280499186173,4cyclictest171rcu_preempt09:47:5714
3280499186173,4cyclictest171rcu_preempt09:47:5714
3279699186141,19cyclictest0-21swapper/1308:48:545
3279699186141,19cyclictest0-21swapper/1308:48:545
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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