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2024-10-07 - 00:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sun Oct 06, 2024 13:02:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1987899254251,2cyclictest0-21swapper/2108:53:2814
1987899254251,2cyclictest0-21swapper/2108:53:2814
1988699229226,2cyclictest0-21swapper/2410:19:5217
1988699229226,2cyclictest0-21swapper/2410:19:5217
1988699229226,2cyclictest0-21swapper/2410:19:5217
1988699229226,2cyclictest0-21swapper/2410:19:5217
1985199222213,7cyclictest0-21swapper/711:16:4737
1985199222213,7cyclictest0-21swapper/711:16:4737
1985199222213,7cyclictest0-21swapper/711:16:4737
1985399220211,6cyclictest0-21swapper/912:39:5539
1985399220211,6cyclictest0-21swapper/912:39:5539
1985399220211,6cyclictest0-21swapper/912:39:5539
199099921610,127cyclictest0-21swapper/3808:55:1832
199099921610,127cyclictest0-21swapper/3808:55:1832
1989799206192,11cyclictest0-21swapper/3312:11:3227
1989799206192,11cyclictest0-21swapper/3312:11:3227
1989799206192,11cyclictest0-21swapper/3312:11:3227
1985199201196,3cyclictest0-21swapper/711:43:0037
1985199201196,3cyclictest0-21swapper/711:43:0037
1985199201196,3cyclictest0-21swapper/711:43:0037
198959919459,114cyclictest24293-21TaskSchedulerSi11:50:1725
198959919459,114cyclictest24293-21TaskSchedulerSi11:50:1725
198959919459,114cyclictest24293-21TaskSchedulerSi11:50:1725
1986199190174,6cyclictest0-21swapper/1511:53:127
1986199190174,6cyclictest0-21swapper/1511:53:127
1986199190174,6cyclictest0-21swapper/1511:53:127
1986199189173,9cyclictest4908-21CPU7
1986199189173,9cyclictest4908-21CPU7
1986199189173,9cyclictest4908-21CPU7
1987899188179,7cyclictest0-21swapper/2112:10:2614
1987899188179,7cyclictest0-21swapper/2112:10:2614
1987899188179,7cyclictest0-21swapper/2112:10:2614
19894991878,167cyclictest0-21swapper/3011:35:1824
19894991878,167cyclictest0-21swapper/3011:35:1824
19894991878,167cyclictest0-21swapper/3011:35:1824
1989099187142,36cyclictest0-21swapper/2609:54:4219
1989099187142,36cyclictest0-21swapper/2609:54:4219
1989099187142,36cyclictest0-21swapper/2609:54:4219
1988899186144,39cyclictest0-21swapper/2511:33:0018
1988899186144,39cyclictest0-21swapper/2511:33:0018
1988899186144,39cyclictest0-21swapper/2511:33:0018
1985399186168,15cyclictest0-21swapper/907:50:0039
1985399186168,15cyclictest0-21swapper/907:50:0039
1985199185172,8cyclictest0-21swapper/712:00:3137
1985199185172,8cyclictest0-21swapper/712:00:3137
1984799185170,13cyclictest0-21swapper/511:04:3135
1984799185170,13cyclictest0-21swapper/511:04:3135
1984799185170,13cyclictest0-21swapper/511:04:3135
1990099183180,2cyclictest0-21swapper/3410:29:0728
1990099183180,2cyclictest0-21swapper/3410:29:0728
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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