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2023-12-04 - 10:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 04, 2023 01:00:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1486499204174,28cyclictest0-21swapper/3423:14:3328
1486499204174,28cyclictest0-21swapper/3423:14:3328
14864991984,147cyclictest18935-21CPU28
14864991984,147cyclictest18935-21CPU28
14864991984,147cyclictest18935-21CPU28
1484599197186,10cyclictest0-21swapper/1822:50:0810
1484599197186,10cyclictest0-21swapper/1822:50:0810
1484599187169,10cyclictest0-21swapper/1822:49:5310
1484599187169,10cyclictest0-21swapper/1822:49:5310
1484599185173,10cyclictest0-21swapper/1823:11:3210
1484599185173,10cyclictest0-21swapper/1823:11:3210
1486399184169,6cyclictest171rcu_preempt00:15:1127
1486399184169,6cyclictest171rcu_preempt00:15:1127
1486399184169,6cyclictest171rcu_preempt00:15:1127
1486399182160,14cyclictest171rcu_preempt23:43:5727
1486399182160,14cyclictest171rcu_preempt23:43:5727
1484999182171,8cyclictest0-21swapper/2100:34:2814
1484999182171,8cyclictest0-21swapper/2100:34:2814
1484999182121,27cyclictest0-21swapper/2122:16:5514
1484999182121,27cyclictest0-21swapper/2122:16:5514
1484999181163,12cyclictest171rcu_preempt22:28:3414
1484999181163,12cyclictest171rcu_preempt22:28:3414
1484999181163,12cyclictest171rcu_preempt22:28:3414
1486399180163,10cyclictest171rcu_preempt00:11:5827
1486399180163,10cyclictest171rcu_preempt00:11:5827
1486399180163,10cyclictest171rcu_preempt00:11:5727
1486399180151,15cyclictest171rcu_preempt21:34:3027
1486399180151,15cyclictest171rcu_preempt21:34:3027
1486399180151,15cyclictest171rcu_preempt21:34:2927
1484999180101,75cyclictest18937-21CPU14
1484999180101,75cyclictest18937-21CPU14
1484999180101,75cyclictest18937-21CPU14
1484999179160,9cyclictest0-21swapper/2123:57:1414
1484999179160,9cyclictest0-21swapper/2123:57:1314
1484999179160,9cyclictest0-21swapper/2123:57:1314
148309917992,75cyclictest11080-21CPU36
148309917992,75cyclictest11080-21CPU36
1486399178160,11cyclictest171rcu_preempt23:32:2127
1486399178160,11cyclictest171rcu_preempt23:32:2127
1486399178156,7cyclictest171rcu_preempt22:05:1827
1486399178156,7cyclictest171rcu_preempt22:05:1827
1484999178169,6cyclictest0-21swapper/2122:40:0214
1484999178169,6cyclictest0-21swapper/2122:40:0214
1484999178165,9cyclictest0-21swapper/2121:37:0414
1484999178165,9cyclictest0-21swapper/2121:37:0414
1484999178165,9cyclictest0-21swapper/2121:37:0414
1484599178167,4cyclictest0-21swapper/1819:18:1810
1484599178167,4cyclictest0-21swapper/1819:18:1810
1486399177144,21cyclictest0-21swapper/3321:19:2527
1486399177144,21cyclictest0-21swapper/3321:19:2527
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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