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2024-07-27 - 03:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 27, 2024 01:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2869499303298,3cyclictest38662-21kworker/u81:2+events_unbound00:10:4417
2869499303298,3cyclictest38662-21kworker/u81:2+events_unbound00:10:4417
2869499303298,3cyclictest38662-21kworker/u81:2+events_unbound00:10:4317
2868099299296,2cyclictest0-21swapper/1222:25:494
2868099299296,2cyclictest0-21swapper/1222:25:494
2868099299296,2cyclictest0-21swapper/1222:25:494
2868399217214,2cyclictest0-21swapper/1521:55:317
2868399217214,2cyclictest0-21swapper/1521:55:307
2868399217214,2cyclictest0-21swapper/1521:55:307
2868299210202,6cyclictest0-21swapper/1422:13:476
2868299210202,6cyclictest0-21swapper/1422:13:476
2869699205180,17cyclictest0-21swapper/2623:46:1319
2869699205180,17cyclictest0-21swapper/2623:46:1319
2867299205197,5cyclictest15980-21CPU35
2867299205197,5cyclictest15980-21CPU35
2867299205197,5cyclictest15980-21CPU35
2867099202181,17cyclictest0-21swapper/321:33:5323
2867099202181,17cyclictest0-21swapper/321:33:5323
2868199197123,70cyclictest4908-21CPU5
2867099197185,7cyclictest0-21swapper/321:51:3123
2867099197185,7cyclictest0-21swapper/321:51:3123
2867099197185,7cyclictest0-21swapper/321:51:3123
2870799195185,8cyclictest0-21swapper/3622:48:0130
2870799195185,8cyclictest0-21swapper/3622:48:0130
2866899195178,12cyclictest0-21swapper/122:05:281
2866899195178,12cyclictest0-21swapper/122:05:281
2870999194120,60cyclictest15981-21CPU31
2870999194120,60cyclictest15981-21CPU31
2870999194120,60cyclictest15981-21CPU31
2869699194190,2cyclictest0-21swapper/2622:40:0219
2869699194190,2cyclictest0-21swapper/2622:40:0119
2869199192176,8cyclictest0-21swapper/2100:09:5214
2869199192176,8cyclictest0-21swapper/2100:09:5214
2869199192176,8cyclictest0-21swapper/2100:09:5214
2869099192158,17cyclictest0-21swapper/2019:45:2613
2869099192158,17cyclictest0-21swapper/2019:45:2613
28686991920,2cyclictest0-21swapper/1721:20:009
28686991920,2cyclictest0-21swapper/1721:20:009
28686991920,2cyclictest0-21swapper/1721:20:009
2869699191184,4cyclictest0-21swapper/2623:43:4519
2869699191184,4cyclictest0-21swapper/2623:43:4519
2869699191184,4cyclictest0-21swapper/2623:43:4519
2869699191139,45cyclictest4632-21CPU19
2869699191139,45cyclictest4632-21CPU19
2869699191139,45cyclictest4632-21CPU19
2869099191141,47cyclictest15985-21CPU13
2869099191141,47cyclictest15985-21CPU13
2869799190178,11cyclictest0-21swapper/2721:57:3120
2869799190178,11cyclictest0-21swapper/2721:57:3120
2869799190178,11cyclictest0-21swapper/2721:57:3020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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