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2019-07-16 - 02:57

Intel(R) Core(TM)2 Duo CPU T7300 @ 2.00GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #6, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 20 highest latencies:
System rack6slot1.osadl.org (updated Thu Mar 28, 2019 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
386399850435cyclictest3896-21sensors10:25:171
386399830422cyclictest29470-21sensors10:15:161
386399822422cyclictest0-21swapper/109:40:181
386399821424cyclictest3540-21syscall08:10:221
386399821420cyclictest2020-21sensors08:00:181
386399815416cyclictest9082-21ssh11:20:191
386399812416cyclictest30367-21snmpd08:04:441
386399805417cyclictest0-21swapper/112:30:181
386399804417cyclictest0-21swapper/108:35:171
386399804413cyclictest30367-21snmpd09:35:181
386399803416cyclictest0-21swapper/107:55:191
386399794409cyclictest0-21swapper/111:25:181
386399791404cyclictest30691-21sensors07:50:201
386399789405cyclictest26713-21sensors07:45:191
386399786408cyclictest9438-21ssh09:45:171
386399781404cyclictest0-21swapper/111:45:191
386399774401cyclictest0-21swapper/111:40:191
386299750438cyclictest372-21sensors11:55:190
386399747384cyclictest3906-21sensors12:00:181
386299743434cyclictest14127-21sensors10:40:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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