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2021-01-26 - 06:40

Intel(R) Core(TM)2 Duo CPU T7300 @ 2.00GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #6, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 50 highest latencies:
System rack6slot1.osadl.org (updated Thu Mar 28, 2019 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
386399850435cyclictest3896-21sensors10:25:171
386399830422cyclictest29470-21sensors10:15:161
386399822422cyclictest0-21swapper/109:40:181
386399821424cyclictest3540-21syscall08:10:221
386399821420cyclictest2020-21sensors08:00:181
386399815416cyclictest9082-21ssh11:20:191
386399812416cyclictest30367-21snmpd08:04:441
386399805417cyclictest0-21swapper/112:30:181
386399804417cyclictest0-21swapper/108:35:171
386399804413cyclictest30367-21snmpd09:35:181
386399803416cyclictest0-21swapper/107:55:191
386399794409cyclictest0-21swapper/111:25:181
386399791404cyclictest30691-21sensors07:50:201
386399789405cyclictest26713-21sensors07:45:191
386399786408cyclictest9438-21ssh09:45:171
386399781404cyclictest0-21swapper/111:45:191
386399774401cyclictest0-21swapper/111:40:191
386299750438cyclictest372-21sensors11:55:190
386399747384cyclictest3906-21sensors12:00:181
386299743434cyclictest14127-21sensors10:40:180
386299742435cyclictest10350-21sensors07:25:190
386299741437cyclictest0-21swapper/010:35:170
386299739433cyclictest0-21swapper/009:15:180
386299738435cyclictest0-21swapper/010:50:190
386299734430cyclictest17572-21sensors10:45:250
386299728429cyclictest2717-21syscall08:09:440
386399726374cyclictest7304-21sensors10:30:171
386299726430cyclictest3753-21context108:05:200
386399725373cyclictest20943-21sensors10:50:191
386299724429cyclictest0-21swapper/009:55:170
386299717424cyclictest13488-21pipe07:35:180
386299715422cyclictest0-21swapper/008:25:180
386399711364cyclictest31235-21sensors11:05:171
386399709365cyclictest10636-21ntp_states10:35:151
386299708417cyclictest30367-21snmpd10:10:090
386299706418cyclictest0-21swapper/007:10:160
386399702361cyclictest30367-21snmpd12:35:381
386399701363cyclictest16462-21sensors07:40:181
386299697417cyclictest0-21swapper/010:00:190
386399690354cyclictest22783-21sensors10:05:181
386299685406cyclictest30367-21snmpd10:25:130
386399675347cyclictest30367-21snmpd08:14:451
386399672346cyclictest19438-21sensors10:00:191
386399669417cyclictest2308-21sensors11:10:181
386299668397cyclictest30367-21snmpd08:39:510
386299656392cyclictest30367-21snmpd07:44:390
386399655339cyclictest30367-21snmpd09:24:591
386399652338cyclictest27784-21sensors11:00:171
386399652337cyclictest30367-21snmpd12:00:311
386299649388cyclictest30367-21snmpd10:05:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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