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2024-11-04 - 22:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Nov 04, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322472600,1sleep032248-22ntp_kernel_pll_11:29:470
189292448,29sleep00-21swapper/007:06:300
19283993628,7cyclictest245950irq/16-enp2s0f010:54:450
190912368,8sleep10-21swapper/107:08:101
19284993434,0cyclictest167950irq/16-i91510:37:511
19284993432,1cyclictest167950irq/16-i91512:04:501
19284993432,1cyclictest167950irq/16-i91511:25:111
19284993432,1cyclictest167950irq/16-i91509:54:421
19284993432,1cyclictest167950irq/16-i91507:29:561
19283993434,0cyclictest245950irq/16-enp2s0f008:53:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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