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2023-02-06 - 07:31

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Feb 06, 2023 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
827524312,23sleep00-21swapper/018:59:210
9624993730,6cyclictest248850irq/16-enp2s0f000:32:020
926623716,13sleep10-21swapper/119:01:121
9624993630,6cyclictest248850irq/16-enp2s0f021:05:300
9625993534,0cyclictest168050irq/16-i91523:37:491
9625993533,1cyclictest168050irq/16-i91522:06:591
9624993534,1cyclictest248850irq/16-enp2s0f020:54:260
9624993534,0cyclictest248850irq/16-enp2s0f023:37:460
9624993534,0cyclictest248850irq/16-enp2s0f021:24:320
9624993534,0cyclictest248850irq/16-enp2s0f019:27:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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