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2026-05-10 - 13:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sun May 10, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2524624513,25sleep00-21swapper/019:04:310
289152430,0sleep00-21swapper/019:32:580
252322428,8sleep10-21swapper/119:04:221
25642993534,0cyclictest246650irq/16-enp2s0f022:39:150
25643993432,1cyclictest168750irq/16-i91523:35:341
25643993432,1cyclictest168750irq/16-i91500:19:391
25642993433,0cyclictest246650irq/16-enp2s0f023:43:410
25642993433,0cyclictest246650irq/16-enp2s0f019:54:420
25642993433,0cyclictest246650irq/16-enp2s0f000:09:360
25642993432,1cyclictest246650irq/16-enp2s0f022:53:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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