You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-05-21 - 18:50
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue May 21, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123822438,8sleep00-21swapper/007:06:070
12552993534,0cyclictest168750irq/16-i91508:46:171
12551993534,0cyclictest271250irq/16-enp2s0f009:43:400
12551993534,0cyclictest271250irq/16-enp2s0f009:17:080
1241523510,17sleep10-21swapper/107:06:261
12552993433,0cyclictest168750irq/16-i91512:10:381
12552993433,0cyclictest168750irq/16-i91510:23:301
12552993433,0cyclictest168750irq/16-i91508:18:531
12552993432,1cyclictest168750irq/16-i91512:12:401
12552993432,1cyclictest168750irq/16-i91509:39:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional