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2025-07-07 - 02:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Jul 07, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300742530,0sleep10-21swapper/121:39:521
161002449,8sleep10-21swapper/119:01:021
163492438,8sleep00-21swapper/019:03:330
16534993728,8cyclictest245950irq/16-enp2s0f021:30:070
16534993628,7cyclictest245950irq/16-enp2s0f023:40:040
16535993534,0cyclictest167950irq/16-i91523:19:561
16535993533,1cyclictest167950irq/16-i91521:00:031
16534993534,0cyclictest245950irq/16-enp2s0f023:19:560
16534993534,0cyclictest245950irq/16-enp2s0f019:56:080
16535993432,1cyclictest167950irq/16-i91522:30:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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