You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-01 - 17:52

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Jun 01, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248552970,0sleep124852-22head10:27:351
184192620,0sleep00-21swapper/008:17:270
281042469,8sleep00-21swapper/007:00:510
2821123812,19sleep10-21swapper/107:01:581
28290993534,0cyclictest248850irq/16-enp2s0f012:12:240
28290993533,1cyclictest248850irq/16-enp2s0f007:44:580
28291993433,0cyclictest168050irq/16-i91511:55:311
28291993432,1cyclictest168050irq/16-i91511:24:371
28291993432,1cyclictest168050irq/16-i91510:45:321
28291993432,1cyclictest168050irq/16-i91509:37:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional