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2023-12-08 - 00:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 07, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
102602590,0sleep00-21swapper/010:58:590
283524414,22sleep00-21swapper/006:54:060
3574993634,1cyclictest248850irq/16-enp2s0f010:01:400
3574993629,6cyclictest248850irq/16-enp2s0f010:37:430
3575993534,0cyclictest168050irq/16-i91510:57:231
3575993533,1cyclictest168050irq/16-i91509:26:331
22132358,8sleep10-21swapper/106:53:491
3575993432,1cyclictest168050irq/16-i91512:23:581
3575993432,1cyclictest168050irq/16-i91510:52:241
3575993432,1cyclictest168050irq/16-i91509:47:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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