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2025-07-09 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Jul 09, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
567924516,21sleep00-21swapper/019:02:550
556624317,19sleep10-21swapper/119:01:501
5922993732,4cyclictest167950irq/16-i91523:47:361
5922993732,4cyclictest167950irq/16-i91500:02:121
5922993731,3cyclictest167950irq/16-i91522:31:231
5922993730,6cyclictest167950irq/16-i91521:00:071
5922993634,1cyclictest167950irq/16-i91520:20:021
5922993632,3cyclictest245950irq/16-enp2s0f019:40:111
5922993632,3cyclictest245950irq/16-enp2s0f019:06:361
5922993631,4cyclictest167950irq/16-i91522:44:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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