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2025-02-07 - 09:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Feb 07, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
506824925,20sleep00-21swapper/019:05:060
50552389,8sleep10-21swapper/119:04:591
5385993533,1cyclictest167950irq/16-i91522:27:491
5384993534,0cyclictest245950irq/16-enp2s0f000:20:460
5385993433,0cyclictest167950irq/16-i91522:45:471
5385993433,0cyclictest167950irq/16-i91500:24:521
5385993432,1cyclictest167950irq/16-i91522:10:581
5385993432,1cyclictest167950irq/16-i91521:44:191
5385993432,1cyclictest167950irq/16-i91521:13:501
5385993432,1cyclictest167950irq/16-i91520:52:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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