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2024-04-25 - 13:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Apr 25, 2024 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146232459,29sleep00-21swapper/019:05:390
1472123914,17sleep10-21swapper/119:06:401
14883993534,0cyclictest271250irq/16-enp2s0f000:14:100
14884993433,0cyclictest168750irq/16-i91521:04:211
14884993432,1cyclictest168750irq/16-i91523:05:201
14884993432,1cyclictest168750irq/16-i91522:57:361
14884993432,1cyclictest168750irq/16-i91521:23:001
14884993432,1cyclictest168750irq/16-i91521:07:551
14884993432,1cyclictest168750irq/16-i91520:28:111
14883993434,0cyclictest271250irq/16-enp2s0f021:44:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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