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2022-05-25 - 00:40

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot2.osadl.org (updated Fri May 20, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16879993931,7cyclictest248850irq/16-enp2s0f020:34:090
164672389,22sleep10-21swapper/119:05:191
16879993729,7cyclictest248850irq/16-enp2s0f020:07:320
164662379,21sleep00-21swapper/019:05:180
16880993533,1cyclictest168050irq/16-i91521:49:071
16880993432,1cyclictest168050irq/16-i91523:54:121
16880993432,1cyclictest168050irq/16-i91523:04:581
16880993432,1cyclictest168050irq/16-i91521:24:081
16880993432,1cyclictest168050irq/16-i91521:04:101
16880993432,1cyclictest168050irq/16-i91520:24:051
16880993432,1cyclictest168050irq/16-i91500:31:481
16880993432,1cyclictest168050irq/16-i91500:26:031
16880993432,1cyclictest168050irq/16-i91500:09:091
16879993434,0cyclictest248850irq/16-enp2s0f020:33:150
16879993432,1cyclictest248850irq/16-enp2s0f023:18:360
16879993432,1cyclictest248850irq/16-enp2s0f022:09:080
16879993432,1cyclictest248850irq/16-enp2s0f020:44:070
16879993432,1cyclictest248850irq/16-enp2s0f019:49:110
16879993432,1cyclictest248850irq/16-enp2s0f019:09:070
16879993432,1cyclictest248850irq/16-enp2s0f000:13:450
16879993426,7cyclictest248850irq/16-enp2s0f019:54:090
16879993426,6cyclictest248850irq/16-enp2s0f019:14:100
16880993333,0cyclictest168050irq/16-i91519:39:161
16880993332,0cyclictest248850irq/16-enp2s0f021:34:061
16880993332,0cyclictest248850irq/16-enp2s0f021:19:051
16880993332,0cyclictest168050irq/16-i91523:49:491
16880993332,0cyclictest168050irq/16-i91523:21:581
16880993332,0cyclictest168050irq/16-i91523:14:061
16880993332,0cyclictest168050irq/16-i91522:56:521
16880993332,0cyclictest168050irq/16-i91522:39:361
16880993332,0cyclictest168050irq/16-i91522:32:391
16880993332,0cyclictest168050irq/16-i91522:24:141
16880993332,0cyclictest168050irq/16-i91522:18:561
16880993332,0cyclictest168050irq/16-i91521:54:101
16880993332,0cyclictest168050irq/16-i91521:44:551
16880993332,0cyclictest168050irq/16-i91521:42:131
16880993332,0cyclictest168050irq/16-i91520:59:091
16880993332,0cyclictest168050irq/16-i91520:53:001
16880993332,0cyclictest168050irq/16-i91520:22:491
16880993332,0cyclictest168050irq/16-i91519:59:041
16880993332,0cyclictest168050irq/16-i91519:25:251
16880993332,0cyclictest168050irq/16-i91519:09:391
16880993332,0cyclictest168050irq/16-i91500:34:051
16880993332,0cyclictest168050irq/16-i91500:14:251
16880993332,0cyclictest168050irq/16-i91500:04:521
16880993331,1cyclictest168050irq/16-i91523:44:001
16880993331,1cyclictest168050irq/16-i91522:59:111
16880993331,1cyclictest168050irq/16-i91522:14:091
16880993331,1cyclictest168050irq/16-i91521:29:081
16880993331,1cyclictest168050irq/16-i91521:16:581
16880993331,1cyclictest168050irq/16-i91520:44:081
16880993331,1cyclictest168050irq/16-i91520:29:131
16880993331,1cyclictest168050irq/16-i91520:14:461
16880993331,1cyclictest168050irq/16-i91519:54:081
16880993331,1cyclictest168050irq/16-i91519:49:051
16880993331,1cyclictest168050irq/16-i91519:30:091
16880993331,1cyclictest168050irq/16-i91500:19:091
16879993332,0cyclictest248850irq/16-enp2s0f023:52:580
16879993332,0cyclictest248850irq/16-enp2s0f023:46:580
16879993332,0cyclictest248850irq/16-enp2s0f023:39:150
16879993332,0cyclictest248850irq/16-enp2s0f023:34:060
16879993332,0cyclictest248850irq/16-enp2s0f023:24:060
16879993332,0cyclictest248850irq/16-enp2s0f023:19:060
16879993332,0cyclictest248850irq/16-enp2s0f023:09:350
16879993332,0cyclictest248850irq/16-enp2s0f023:03:580
16879993332,0cyclictest248850irq/16-enp2s0f022:39:130
16879993332,0cyclictest248850irq/16-enp2s0f022:24:140
16879993332,0cyclictest248850irq/16-enp2s0f022:18:560
16879993332,0cyclictest248850irq/16-enp2s0f021:59:070
16879993332,0cyclictest248850irq/16-enp2s0f021:54:100
16879993332,0cyclictest248850irq/16-enp2s0f021:49:070
16879993332,0cyclictest248850irq/16-enp2s0f021:36:550
16879993332,0cyclictest248850irq/16-enp2s0f021:24:130
16879993332,0cyclictest248850irq/16-enp2s0f021:19:120
16879993332,0cyclictest248850irq/16-enp2s0f021:09:050
16879993332,0cyclictest248850irq/16-enp2s0f020:59:150
16879993332,0cyclictest248850irq/16-enp2s0f020:52:530
16879993332,0cyclictest248850irq/16-enp2s0f020:40:240
16879993332,0cyclictest248850irq/16-enp2s0f019:44:130
16879993332,0cyclictest248850irq/16-enp2s0f019:39:110
16879993332,0cyclictest248850irq/16-enp2s0f000:35:060
16879993332,0cyclictest248850irq/16-enp2s0f000:29:100
16879993332,0cyclictest248850irq/16-enp2s0f000:14:500
16879993332,0cyclictest248850irq/16-enp2s0f000:04:520
16879993331,1cyclictest248850irq/16-enp2s0f023:54:120
16879993331,1cyclictest248850irq/16-enp2s0f022:59:080
16879993331,1cyclictest248850irq/16-enp2s0f022:49:010
16879993331,1cyclictest248850irq/16-enp2s0f022:44:100
16879993331,1cyclictest248850irq/16-enp2s0f022:34:110
16879993331,1cyclictest248850irq/16-enp2s0f022:29:290
16879993331,1cyclictest248850irq/16-enp2s0f022:14:100
16879993331,1cyclictest248850irq/16-enp2s0f021:44:100
16879993331,1cyclictest248850irq/16-enp2s0f021:42:250
16879993331,1cyclictest248850irq/16-enp2s0f021:32:130
16879993331,1cyclictest248850irq/16-enp2s0f021:14:090
16879993331,1cyclictest248850irq/16-enp2s0f020:24:050
16879993331,1cyclictest248850irq/16-enp2s0f020:19:080
16879993331,1cyclictest248850irq/16-enp2s0f020:14:460
16879993331,1cyclictest248850irq/16-enp2s0f020:09:090
16879993331,1cyclictest248850irq/16-enp2s0f019:24:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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