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2022-09-25 - 07:57
/usr/bin/Xorg /usr/bin/Xorg

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot2.osadl.org (updated Sun Sep 25, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
771925225,8sleep10-21swapper/119:05:301
77832408,8sleep00-21swapper/019:06:090
7894993533,1cyclictest168050irq/16-i91520:21:511
7893993534,0cyclictest248850irq/16-enp2s0f022:23:320
7893993534,0cyclictest248850irq/16-enp2s0f020:50:400
7894993433,0cyclictest248850irq/16-enp2s0f021:01:571
7894993433,0cyclictest168050irq/16-i91519:30:101
7894993432,1cyclictest168050irq/16-i91522:57:091
7894993432,1cyclictest168050irq/16-i91522:42:001
7894993432,1cyclictest168050irq/16-i91520:56:511
7894993432,1cyclictest168050irq/16-i91520:01:521
7893993432,1cyclictest248850irq/16-enp2s0f023:30:130
7893993432,1cyclictest248850irq/16-enp2s0f023:18:470
7893993432,1cyclictest248850irq/16-enp2s0f022:17:080
7893993432,1cyclictest248850irq/16-enp2s0f021:47:000
7893993432,1cyclictest248850irq/16-enp2s0f021:10:050
7893993432,1cyclictest248850irq/16-enp2s0f020:36:510
7893993432,1cyclictest248850irq/16-enp2s0f019:51:570
7893993432,1cyclictest248850irq/16-enp2s0f019:36:540
7893993432,1cyclictest248850irq/16-enp2s0f019:26:550
7893993432,1cyclictest248850irq/16-enp2s0f019:21:560
7893993432,1cyclictest248850irq/16-enp2s0f000:34:300
7894993333,0cyclictest168050irq/16-i91522:39:371
7894993332,0cyclictest248850irq/16-enp2s0f021:17:031
7894993332,0cyclictest248850irq/16-enp2s0f000:04:181
7894993332,0cyclictest168050irq/16-i91523:59:171
7894993332,0cyclictest168050irq/16-i91523:23:051
7894993332,0cyclictest168050irq/16-i91523:19:171
7894993332,0cyclictest168050irq/16-i91522:54:591
7894993332,0cyclictest168050irq/16-i91522:11:531
7894993332,0cyclictest168050irq/16-i91522:06:351
7894993332,0cyclictest168050irq/16-i91521:58:551
7894993332,0cyclictest168050irq/16-i91521:12:021
7894993332,0cyclictest168050irq/16-i91520:42:091
7894993332,0cyclictest168050irq/16-i91520:14:571
7894993332,0cyclictest168050irq/16-i91520:08:021
7894993332,0cyclictest168050irq/16-i91519:46:541
7894993332,0cyclictest168050irq/16-i91519:42:321
7894993332,0cyclictest168050irq/16-i91519:23:201
7894993332,0cyclictest168050irq/16-i91519:13:211
7894993332,0cyclictest168050irq/16-i91519:06:511
7894993332,0cyclictest168050irq/16-i91500:28:291
7894993331,1cyclictest248850irq/16-enp2s0f023:02:411
7894993331,1cyclictest248850irq/16-enp2s0f020:51:521
7894993331,1cyclictest168050irq/16-i91523:31:591
7894993331,1cyclictest168050irq/16-i91522:32:411
7894993331,1cyclictest168050irq/16-i91522:21:521
7894993331,1cyclictest168050irq/16-i91521:47:181
7894993331,1cyclictest168050irq/16-i91521:41:591
7894993331,1cyclictest168050irq/16-i91521:26:561
7894993331,1cyclictest168050irq/16-i91521:09:371
7894993331,1cyclictest168050irq/16-i91520:28:261
7894993331,1cyclictest168050irq/16-i91519:56:231
7894993331,1cyclictest168050irq/16-i91500:21:581
7893993333,0cyclictest248850irq/16-enp2s0f000:06:520
7893993332,0cyclictest248850irq/16-enp2s0f023:42:000
7893993332,0cyclictest248850irq/16-enp2s0f023:31:410
7893993332,0cyclictest248850irq/16-enp2s0f023:02:010
7893993332,0cyclictest248850irq/16-enp2s0f022:53:350
7893993332,0cyclictest248850irq/16-enp2s0f022:47:290
7893993332,0cyclictest248850irq/16-enp2s0f022:26:490
7893993332,0cyclictest248850irq/16-enp2s0f022:11:570
7893993332,0cyclictest248850irq/16-enp2s0f022:07:360
7893993332,0cyclictest248850irq/16-enp2s0f021:59:250
7893993332,0cyclictest248850irq/16-enp2s0f021:45:010
7893993332,0cyclictest248850irq/16-enp2s0f021:33:310
7893993332,0cyclictest248850irq/16-enp2s0f021:21:590
7893993332,0cyclictest248850irq/16-enp2s0f021:01:420
7893993332,0cyclictest248850irq/16-enp2s0f020:06:510
7893993332,0cyclictest248850irq/16-enp2s0f020:02:000
7893993332,0cyclictest248850irq/16-enp2s0f019:57:020
7893993332,0cyclictest248850irq/16-enp2s0f019:46:550
7893993332,0cyclictest248850irq/16-enp2s0f019:36:170
7893993332,0cyclictest248850irq/16-enp2s0f019:16:500
7893993332,0cyclictest248850irq/16-enp2s0f019:06:450
7893993332,0cyclictest248850irq/16-enp2s0f000:27:050
7893993332,0cyclictest248850irq/16-enp2s0f000:21:590
7893993332,0cyclictest248850irq/16-enp2s0f000:12:000
7893993332,0cyclictest248850irq/16-enp2s0f000:03:210
7893993331,1cyclictest248850irq/16-enp2s0f023:57:000
7893993331,1cyclictest248850irq/16-enp2s0f023:46:530
7893993331,1cyclictest248850irq/16-enp2s0f023:21:560
7893993331,1cyclictest248850irq/16-enp2s0f023:12:570
7893993331,1cyclictest248850irq/16-enp2s0f022:57:030
7893993331,1cyclictest248850irq/16-enp2s0f022:42:020
7893993331,1cyclictest248850irq/16-enp2s0f022:36:560
7893993331,1cyclictest248850irq/16-enp2s0f022:32:010
7893993331,1cyclictest248850irq/16-enp2s0f022:01:550
7893993331,1cyclictest248850irq/16-enp2s0f021:51:560
7893993331,1cyclictest248850irq/16-enp2s0f021:36:540
7893993331,1cyclictest248850irq/16-enp2s0f021:29:480
7893993331,1cyclictest248850irq/16-enp2s0f021:17:010
7893993331,1cyclictest248850irq/16-enp2s0f021:11:560
7893993331,1cyclictest248850irq/16-enp2s0f020:41:550
7893993331,1cyclictest248850irq/16-enp2s0f020:32:000
7893993331,1cyclictest248850irq/16-enp2s0f020:27:020
7893993331,1cyclictest248850irq/16-enp2s0f020:16:530
7893993331,1cyclictest248850irq/16-enp2s0f019:41:560
7893993331,1cyclictest248850irq/16-enp2s0f019:12:020
7894993232,0cyclictest168050irq/16-i91523:46:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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