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2023-02-02 - 16:33

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot2.osadl.org (updated Thu Feb 02, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218602640,1sleep00-21swapper/009:19:370
1330925120,23sleep00-21swapper/007:00:570
13698994032,6cyclictest248850irq/16-enp2s0f008:14:440
135562389,21sleep10-21swapper/107:03:261
13698993731,5cyclictest248850irq/16-enp2s0f009:34:440
13698993731,0cyclictest248850irq/16-enp2s0f007:29:050
13699993634,1cyclictest168050irq/16-i91512:14:381
13698993635,0cyclictest248850irq/16-enp2s0f011:06:050
13698993634,1cyclictest248850irq/16-enp2s0f010:05:340
13698993634,1cyclictest248850irq/16-enp2s0f008:29:410
13698993631,4cyclictest248850irq/16-enp2s0f011:19:420
13698993534,0cyclictest248850irq/16-enp2s0f012:33:390
13698993534,0cyclictest248850irq/16-enp2s0f011:34:380
13698993534,0cyclictest248850irq/16-enp2s0f011:09:420
13698993534,0cyclictest248850irq/16-enp2s0f010:27:410
13698993533,1cyclictest248850irq/16-enp2s0f012:14:300
13698993533,1cyclictest248850irq/16-enp2s0f011:44:320
13698993533,1cyclictest248850irq/16-enp2s0f009:25:260
13698993533,1cyclictest248850irq/16-enp2s0f007:51:570
13698993533,1cyclictest248850irq/16-enp2s0f007:39:370
13699993434,0cyclictest248850irq/16-enp2s0f009:37:401
13699993434,0cyclictest168050irq/16-i91508:21:511
13699993433,1cyclictest168050irq/16-i91511:09:591
13699993433,0cyclictest248850irq/16-enp2s0f011:04:121
13699993433,0cyclictest168050irq/16-i91511:35:491
13699993433,0cyclictest168050irq/16-i91511:21:041
13699993433,0cyclictest168050irq/16-i91509:33:591
13699993433,0cyclictest168050irq/16-i91508:27:041
13699993432,1cyclictest248850irq/16-enp2s0f012:29:341
13699993432,1cyclictest248850irq/16-enp2s0f010:04:411
13699993432,1cyclictest168050irq/16-i91511:49:391
13699993432,1cyclictest168050irq/16-i91511:44:311
13699993432,1cyclictest168050irq/16-i91511:39:331
13699993432,1cyclictest168050irq/16-i91509:09:381
13699993432,1cyclictest168050irq/16-i91508:59:511
13699993432,1cyclictest168050irq/16-i91508:49:391
13699993432,1cyclictest168050irq/16-i91508:12:501
13699993432,1cyclictest168050irq/16-i91507:52:141
13699993432,0cyclictest168050irq/16-i91510:49:321
13698993434,0cyclictest248850irq/16-enp2s0f011:41:090
13698993434,0cyclictest248850irq/16-enp2s0f011:24:210
13698993434,0cyclictest248850irq/16-enp2s0f009:49:000
13698993434,0cyclictest248850irq/16-enp2s0f008:49:390
13698993434,0cyclictest248850irq/16-enp2s0f008:01:320
13698993433,0cyclictest248850irq/16-enp2s0f009:40:440
13698993433,0cyclictest248850irq/16-enp2s0f008:12:260
13698993432,1cyclictest248850irq/16-enp2s0f012:19:330
13698993432,1cyclictest248850irq/16-enp2s0f012:09:360
13698993432,1cyclictest248850irq/16-enp2s0f011:49:330
13698993432,1cyclictest248850irq/16-enp2s0f011:29:300
13698993432,1cyclictest248850irq/16-enp2s0f011:14:310
13698993432,1cyclictest248850irq/16-enp2s0f010:54:380
13698993432,1cyclictest248850irq/16-enp2s0f010:44:380
13698993432,1cyclictest248850irq/16-enp2s0f010:40:320
13698993432,1cyclictest248850irq/16-enp2s0f010:09:440
13698993432,1cyclictest248850irq/16-enp2s0f009:54:400
13698993432,1cyclictest248850irq/16-enp2s0f009:49:350
13698993432,1cyclictest248850irq/16-enp2s0f009:09:390
13698993432,1cyclictest248850irq/16-enp2s0f008:59:400
13698993432,1cyclictest248850irq/16-enp2s0f008:44:370
13698993432,1cyclictest248850irq/16-enp2s0f008:24:410
13698993432,1cyclictest248850irq/16-enp2s0f008:04:380
13698993432,1cyclictest248850irq/16-enp2s0f007:54:400
13698993432,1cyclictest248850irq/16-enp2s0f007:29:380
13698993432,1cyclictest248850irq/16-enp2s0f007:09:370
13698993432,1cyclictest248850irq/16-enp2s0f007:06:370
13699993333,0cyclictest248850irq/16-enp2s0f009:49:371
13699993333,0cyclictest168050irq/16-i91511:29:291
13699993333,0cyclictest168050irq/16-i91509:21:411
13699993332,0cyclictest248850irq/16-enp2s0f012:08:231
13699993332,0cyclictest248850irq/16-enp2s0f010:09:421
13699993332,0cyclictest168050irq/16-i91512:24:381
13699993332,0cyclictest168050irq/16-i91512:09:191
13699993332,0cyclictest168050irq/16-i91510:34:321
13699993332,0cyclictest168050irq/16-i91509:39:391
13699993332,0cyclictest168050irq/16-i91509:24:341
13699993332,0cyclictest168050irq/16-i91508:55:431
13699993332,0cyclictest168050irq/16-i91508:04:381
13699993332,0cyclictest168050irq/16-i91507:54:351
13699993332,0cyclictest168050irq/16-i91507:36:111
13699993332,0cyclictest168050irq/16-i91507:20:171
13699993332,0cyclictest168050irq/16-i91507:16:371
13699993331,1cyclictest248850irq/16-enp2s0f011:24:321
13699993331,1cyclictest248850irq/16-enp2s0f011:14:321
13699993331,1cyclictest248850irq/16-enp2s0f007:24:501
13699993331,1cyclictest190450irq/16-nvkm08:29:371
13699993331,1cyclictest190450irq/16-nvkm07:44:401
13699993331,1cyclictest168050irq/16-i91512:19:311
13699993331,1cyclictest168050irq/16-i91511:04:401
13699993331,1cyclictest168050irq/16-i91510:49:181
13699993331,1cyclictest168050irq/16-i91509:44:431
13699993331,1cyclictest168050irq/16-i91508:44:421
13699993331,1cyclictest168050irq/16-i91508:14:381
13699993331,1cyclictest168050irq/16-i91507:59:371
13699993331,1cyclictest168050irq/16-i91507:31:321
13699993331,1cyclictest168050irq/16-i91507:04:431
13698993333,0cyclictest248850irq/16-enp2s0f012:24:200
13698993333,0cyclictest248850irq/16-enp2s0f007:14:190
13698993332,0cyclictest248850irq/16-enp2s0f012:04:460
13698993332,0cyclictest248850irq/16-enp2s0f011:54:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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