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2023-06-05 - 23:14

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot2.osadl.org (updated Mon Jun 05, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307462580,0sleep10-21swapper/111:08:031
2148124818,22sleep00-21swapper/006:58:210
21901993533,1cyclictest248850irq/16-enp2s0f011:20:440
218142358,19sleep10-21swapper/107:01:481
21902993434,0cyclictest168050irq/16-i91508:48:421
21902993433,0cyclictest168050irq/16-i91507:06:521
21902993432,1cyclictest248850irq/16-enp2s0f011:31:031
21902993432,1cyclictest168050irq/16-i91510:16:361
21902993432,1cyclictest168050irq/16-i91510:06:511
21902993432,1cyclictest168050irq/16-i91510:01:351
21901993434,0cyclictest248850irq/16-enp2s0f007:44:570
21901993433,0cyclictest248850irq/16-enp2s0f008:52:200
21901993432,1cyclictest248850irq/16-enp2s0f010:52:210
21901993432,1cyclictest248850irq/16-enp2s0f010:20:000
21901993432,1cyclictest248850irq/16-enp2s0f009:59:000
21901993432,1cyclictest248850irq/16-enp2s0f009:22:300
21901993432,1cyclictest248850irq/16-enp2s0f008:57:220
21901993432,1cyclictest248850irq/16-enp2s0f008:12:310
21901993432,1cyclictest248850irq/16-enp2s0f007:37:260
21901993432,1cyclictest248850irq/16-enp2s0f007:12:320
21901993432,1cyclictest248850irq/16-enp2s0f007:02:240
21901993432,1cyclictest168050irq/16-i91509:47:260
21901993432,0cyclictest248850irq/16-enp2s0f008:31:520
21901993430,0cyclictest168050irq/16-i91512:04:340
21902993332,0cyclictest248850irq/16-enp2s0f007:24:291
21902993332,0cyclictest168050irq/16-i91512:15:541
21902993332,0cyclictest168050irq/16-i91511:57:261
21902993332,0cyclictest168050irq/16-i91511:25:451
21902993332,0cyclictest168050irq/16-i91511:12:281
21902993332,0cyclictest168050irq/16-i91510:48:001
21902993332,0cyclictest168050irq/16-i91510:25:351
21902993332,0cyclictest168050irq/16-i91510:18:151
21902993332,0cyclictest168050irq/16-i91509:55:051
21902993332,0cyclictest168050irq/16-i91509:47:251
21902993332,0cyclictest168050irq/16-i91509:03:081
21902993332,0cyclictest168050irq/16-i91508:57:201
21902993332,0cyclictest168050irq/16-i91508:31:501
21902993332,0cyclictest168050irq/16-i91508:24:001
21902993332,0cyclictest168050irq/16-i91507:27:151
21902993331,1cyclictest168050irq/16-i91512:20:351
21902993331,1cyclictest168050irq/16-i91512:10:531
21902993331,1cyclictest168050irq/16-i91511:52:271
21902993331,1cyclictest168050irq/16-i91511:48:351
21902993331,1cyclictest168050irq/16-i91511:37:291
21902993331,1cyclictest168050irq/16-i91510:37:181
21902993331,1cyclictest168050irq/16-i91510:08:331
21902993331,1cyclictest168050irq/16-i91509:42:181
21902993331,1cyclictest168050irq/16-i91509:32:281
21902993331,1cyclictest168050irq/16-i91509:22:271
21902993331,1cyclictest168050irq/16-i91508:34:351
21902993331,1cyclictest168050irq/16-i91508:12:321
21902993331,1cyclictest168050irq/16-i91508:07:301
21902993331,1cyclictest168050irq/16-i91507:53:591
21902993331,1cyclictest168050irq/16-i91507:16:121
21901993333,0cyclictest248850irq/16-enp2s0f009:43:490
21901993332,0cyclictest248850irq/16-enp2s0f011:52:220
21901993332,0cyclictest248850irq/16-enp2s0f011:47:240
21901993332,0cyclictest248850irq/16-enp2s0f010:57:270
21901993332,0cyclictest248850irq/16-enp2s0f010:37:230
21901993332,0cyclictest248850irq/16-enp2s0f010:22:180
21901993332,0cyclictest248850irq/16-enp2s0f010:14:380
21901993332,0cyclictest248850irq/16-enp2s0f010:11:000
21901993332,0cyclictest248850irq/16-enp2s0f009:35:220
21901993332,0cyclictest248850irq/16-enp2s0f009:12:350
21901993332,0cyclictest248850irq/16-enp2s0f009:07:320
21901993332,0cyclictest248850irq/16-enp2s0f009:02:390
21901993332,0cyclictest248850irq/16-enp2s0f008:47:270
21901993332,0cyclictest248850irq/16-enp2s0f008:40:070
21901993332,0cyclictest248850irq/16-enp2s0f008:32:210
21901993332,0cyclictest248850irq/16-enp2s0f008:19:010
21901993332,0cyclictest248850irq/16-enp2s0f007:57:150
21901993332,0cyclictest168050irq/16-i91511:07:210
21901993331,1cyclictest248850irq/16-enp2s0f012:27:230
21901993331,1cyclictest248850irq/16-enp2s0f012:22:260
21901993331,1cyclictest248850irq/16-enp2s0f012:17:290
21901993331,1cyclictest248850irq/16-enp2s0f011:57:220
21901993331,1cyclictest248850irq/16-enp2s0f011:04:080
21901993331,1cyclictest248850irq/16-enp2s0f010:27:510
21901993331,1cyclictest248850irq/16-enp2s0f009:37:230
21901993331,1cyclictest248850irq/16-enp2s0f008:42:240
21901993331,1cyclictest248850irq/16-enp2s0f008:22:210
21901993331,1cyclictest248850irq/16-enp2s0f008:07:270
21901993331,1cyclictest248850irq/16-enp2s0f008:02:260
21901993331,1cyclictest248850irq/16-enp2s0f007:32:330
21901993331,1cyclictest248850irq/16-enp2s0f007:18:350
21901993331,1cyclictest248850irq/16-enp2s0f007:07:290
21902993232,0cyclictest248850irq/16-enp2s0f009:07:211
21902993232,0cyclictest168050irq/16-i91512:03:061
21902993232,0cyclictest168050irq/16-i91511:02:221
21902993232,0cyclictest168050irq/16-i91508:17:261
21902993231,0cyclictest248850irq/16-enp2s0f011:42:191
21902993231,0cyclictest248850irq/16-enp2s0f007:42:191
21902993231,0cyclictest248850irq/16-enp2s0f007:32:061
21902993231,0cyclictest168050irq/16-i91512:22:171
21902993231,0cyclictest168050irq/16-i91511:32:261
21902993231,0cyclictest168050irq/16-i91511:17:321
21902993231,0cyclictest168050irq/16-i91510:52:301
21902993231,0cyclictest168050irq/16-i91510:42:271
21902993231,0cyclictest168050irq/16-i91510:32:371
21902993231,0cyclictest168050irq/16-i91510:27:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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