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2023-01-27 - 15:15

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot2.osadl.org (updated Fri Jan 27, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156472610,0sleep10-21swapper/107:59:251
308882458,8sleep00-21swapper/006:59:430
3137024015,18sleep10-21swapper/107:02:081
31648993829,8cyclictest248850irq/16-enp2s0f011:39:390
31651993535,0cyclictest168050irq/16-i91509:09:151
31648993533,1cyclictest248850irq/16-enp2s0f009:49:230
31648993533,1cyclictest190450irq/16-nvkm07:04:420
31648993527,7cyclictest248850irq/16-enp2s0f012:19:240
31648993525,9cyclictest248850irq/16-enp2s0f010:57:300
31651993434,0cyclictest248850irq/16-enp2s0f011:17:581
31651993434,0cyclictest168050irq/16-i91511:19:371
31651993434,0cyclictest168050irq/16-i91510:45:381
31651993433,0cyclictest190450irq/16-nvkm10:13:281
31651993433,0cyclictest168050irq/16-i91512:04:251
31651993433,0cyclictest168050irq/16-i91510:34:261
31651993433,0cyclictest168050irq/16-i91509:59:581
31651993432,1cyclictest248850irq/16-enp2s0f010:54:541
31651993432,1cyclictest248850irq/16-enp2s0f010:49:451
31651993432,1cyclictest248850irq/16-enp2s0f007:09:461
31651993432,1cyclictest168050irq/16-i91512:26:221
31651993432,1cyclictest168050irq/16-i91512:09:491
31651993432,1cyclictest168050irq/16-i91510:29:451
31651993432,1cyclictest168050irq/16-i91510:24:471
31651993432,1cyclictest168050irq/16-i91509:09:361
31651993432,1cyclictest168050irq/16-i91508:44:501
31651993432,1cyclictest168050irq/16-i91508:29:461
31648993434,0cyclictest248850irq/16-enp2s0f011:59:200
31648993434,0cyclictest248850irq/16-enp2s0f010:41:180
31648993434,0cyclictest248850irq/16-enp2s0f009:10:560
31648993434,0cyclictest248850irq/16-enp2s0f008:00:420
31648993434,0cyclictest248850irq/16-enp2s0f007:20:370
31648993433,0cyclictest248850irq/16-enp2s0f011:29:490
31648993433,0cyclictest248850irq/16-enp2s0f010:59:550
31648993433,0cyclictest248850irq/16-enp2s0f010:11:060
31648993433,0cyclictest248850irq/16-enp2s0f008:54:460
31648993433,0cyclictest248850irq/16-enp2s0f007:42:350
31648993433,0cyclictest168050irq/16-i91507:26:220
31648993432,1cyclictest248850irq/16-enp2s0f012:24:370
31648993432,1cyclictest248850irq/16-enp2s0f012:19:420
31648993432,1cyclictest248850irq/16-enp2s0f012:09:410
31648993432,1cyclictest248850irq/16-enp2s0f012:04:460
31648993432,1cyclictest248850irq/16-enp2s0f011:34:380
31648993432,1cyclictest248850irq/16-enp2s0f010:44:440
31648993432,1cyclictest248850irq/16-enp2s0f010:34:400
31648993432,1cyclictest248850irq/16-enp2s0f010:04:420
31648993432,1cyclictest248850irq/16-enp2s0f009:34:420
31648993432,1cyclictest248850irq/16-enp2s0f009:14:480
31648993432,1cyclictest248850irq/16-enp2s0f008:49:400
31648993432,1cyclictest248850irq/16-enp2s0f008:29:460
31648993432,1cyclictest248850irq/16-enp2s0f008:09:440
31648993432,1cyclictest248850irq/16-enp2s0f007:44:480
31648993432,1cyclictest248850irq/16-enp2s0f007:34:430
31651993333,0cyclictest168050irq/16-i91511:34:291
31651993333,0cyclictest168050irq/16-i91509:21:201
31651993333,0cyclictest168050irq/16-i91507:21:571
31651993332,1cyclictest248850irq/16-enp2s0f011:04:311
31651993332,0cyclictest248850irq/16-enp2s0f012:19:561
31651993332,0cyclictest248850irq/16-enp2s0f009:54:411
31651993332,0cyclictest248850irq/16-enp2s0f009:39:231
31651993332,0cyclictest248850irq/16-enp2s0f009:29:521
31651993332,0cyclictest248850irq/16-enp2s0f008:34:551
31651993332,0cyclictest248850irq/16-enp2s0f008:07:041
31651993332,0cyclictest248850irq/16-enp2s0f007:49:411
31651993332,0cyclictest248850irq/16-enp2s0f007:39:461
31651993332,0cyclictest168050irq/16-i91512:29:401
31651993332,0cyclictest168050irq/16-i91511:29:471
31651993332,0cyclictest168050irq/16-i91510:23:051
31651993332,0cyclictest168050irq/16-i91510:14:481
31651993332,0cyclictest168050irq/16-i91509:44:451
31651993332,0cyclictest168050irq/16-i91509:14:471
31651993332,0cyclictest168050irq/16-i91508:39:541
31651993332,0cyclictest168050irq/16-i91508:28:041
31651993332,0cyclictest168050irq/16-i91508:19:421
31651993332,0cyclictest168050irq/16-i91507:45:131
31651993332,0cyclictest168050irq/16-i91507:36:081
31651993332,0cyclictest168050irq/16-i91507:26:541
31651993331,1cyclictest168050irq/16-i91511:59:481
31651993331,1cyclictest168050irq/16-i91511:54:381
31651993331,1cyclictest168050irq/16-i91511:39:361
31651993331,1cyclictest168050irq/16-i91509:39:471
31651993331,1cyclictest168050irq/16-i91508:19:071
31651993331,1cyclictest168050irq/16-i91508:09:421
31651993331,1cyclictest168050irq/16-i91507:29:471
31651993331,1cyclictest168050irq/16-i91507:17:021
31651993331,1cyclictest168050irq/16-i91507:05:421
31648993333,0cyclictest248850irq/16-enp2s0f008:19:530
31648993332,0cyclictest248850irq/16-enp2s0f011:59:290
31648993332,0cyclictest248850irq/16-enp2s0f011:49:390
31648993332,0cyclictest248850irq/16-enp2s0f011:44:410
31648993332,0cyclictest248850irq/16-enp2s0f011:25:370
31648993332,0cyclictest248850irq/16-enp2s0f011:19:460
31648993332,0cyclictest248850irq/16-enp2s0f011:14:300
31648993332,0cyclictest248850irq/16-enp2s0f011:04:440
31648993332,0cyclictest248850irq/16-enp2s0f009:59:420
31648993332,0cyclictest248850irq/16-enp2s0f009:53:110
31648993332,0cyclictest248850irq/16-enp2s0f009:39:330
31648993332,0cyclictest248850irq/16-enp2s0f009:29:520
31648993332,0cyclictest248850irq/16-enp2s0f009:24:250
31648993332,0cyclictest248850irq/16-enp2s0f008:39:090
31648993332,0cyclictest248850irq/16-enp2s0f008:14:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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