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2022-06-30 - 18:23

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot2.osadl.org (updated Thu Jun 30, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67002459,28sleep00-21swapper/007:05:540
65892438,8sleep10-21swapper/107:04:451
6985993533,1cyclictest248850irq/16-enp2s0f008:06:070
6986993433,0cyclictest248850irq/16-enp2s0f007:08:431
6986993432,1cyclictest248850irq/16-enp2s0f012:20:461
6986993432,1cyclictest248850irq/16-enp2s0f010:33:021
6986993432,1cyclictest248850irq/16-enp2s0f009:28:281
6986993432,1cyclictest248850irq/16-enp2s0f009:14:311
6986993432,1cyclictest248850irq/16-enp2s0f008:56:271
6986993432,1cyclictest248850irq/16-enp2s0f008:33:241
6986993432,1cyclictest248850irq/16-enp2s0f008:18:251
6986993432,1cyclictest168050irq/16-i91511:33:091
6986993432,1cyclictest168050irq/16-i91511:23:221
6986993432,1cyclictest168050irq/16-i91510:08:001
6986993432,1cyclictest168050irq/16-i91508:38:301
6986993432,1cyclictest168050irq/16-i91507:43:221
6985993433,0cyclictest248850irq/16-enp2s0f009:27:100
6985993432,1cyclictest248850irq/16-enp2s0f010:21:550
6985993432,1cyclictest248850irq/16-enp2s0f010:14:010
6985993432,1cyclictest248850irq/16-enp2s0f009:53:270
6985993432,1cyclictest248850irq/16-enp2s0f009:48:250
6985993432,1cyclictest248850irq/16-enp2s0f009:08:260
6985993432,1cyclictest248850irq/16-enp2s0f008:53:240
6985993432,1cyclictest248850irq/16-enp2s0f008:13:270
6985993432,1cyclictest248850irq/16-enp2s0f007:58:220
6985993432,1cyclictest248850irq/16-enp2s0f007:38:290
6985993432,1cyclictest248850irq/16-enp2s0f007:20:330
6986993333,0cyclictest168050irq/16-i91512:31:401
6986993332,1cyclictest168050irq/16-i91508:13:271
6986993332,0cyclictest248850irq/16-enp2s0f012:09:141
6986993332,0cyclictest248850irq/16-enp2s0f009:58:241
6986993332,0cyclictest248850irq/16-enp2s0f009:48:261
6986993332,0cyclictest248850irq/16-enp2s0f009:09:351
6986993332,0cyclictest248850irq/16-enp2s0f008:08:241
6986993332,0cyclictest248850irq/16-enp2s0f008:03:221
6986993332,0cyclictest248850irq/16-enp2s0f007:58:471
6986993332,0cyclictest190450irq/16-nvkm12:03:111
6986993332,0cyclictest168050irq/16-i91511:50:011
6986993332,0cyclictest168050irq/16-i91511:46:511
6986993332,0cyclictest168050irq/16-i91511:08:271
6986993332,0cyclictest168050irq/16-i91510:52:551
6986993332,0cyclictest168050irq/16-i91510:43:311
6986993332,0cyclictest168050irq/16-i91507:54:001
6986993332,0cyclictest168050irq/16-i91507:38:321
6986993332,0cyclictest168050irq/16-i91507:36:021
6986993331,1cyclictest248850irq/16-enp2s0f010:53:261
6986993331,1cyclictest248850irq/16-enp2s0f010:33:291
6986993331,1cyclictest248850irq/16-enp2s0f010:26:001
6986993331,1cyclictest248850irq/16-enp2s0f010:13:271
6986993331,1cyclictest248850irq/16-enp2s0f009:53:281
6986993331,1cyclictest248850irq/16-enp2s0f009:21:501
6986993331,1cyclictest248850irq/16-enp2s0f007:18:261
6986993331,1cyclictest168050irq/16-i91511:53:231
6986993331,1cyclictest168050irq/16-i91511:17:301
6986993331,1cyclictest168050irq/16-i91511:17:301
6986993331,1cyclictest168050irq/16-i91511:03:201
6986993331,1cyclictest168050irq/16-i91510:58:221
6986993331,1cyclictest168050irq/16-i91510:08:251
6986993331,1cyclictest168050irq/16-i91509:28:001
6986993331,1cyclictest168050irq/16-i91509:03:331
6986993331,1cyclictest168050irq/16-i91508:48:251
6986993331,1cyclictest168050irq/16-i91508:28:211
6986993331,1cyclictest168050irq/16-i91507:23:231
6986993330,0cyclictest168050irq/16-i91512:13:251
6985993332,1cyclictest248850irq/16-enp2s0f007:52:480
6985993332,1cyclictest248850irq/16-enp2s0f007:13:250
6985993332,0cyclictest248850irq/16-enp2s0f012:13:130
6985993332,0cyclictest248850irq/16-enp2s0f011:58:230
6985993332,0cyclictest248850irq/16-enp2s0f011:53:240
6985993332,0cyclictest248850irq/16-enp2s0f011:43:300
6985993332,0cyclictest248850irq/16-enp2s0f011:36:440
6985993332,0cyclictest248850irq/16-enp2s0f011:30:000
6985993332,0cyclictest248850irq/16-enp2s0f011:08:240
6985993332,0cyclictest248850irq/16-enp2s0f011:04:320
6985993332,0cyclictest248850irq/16-enp2s0f010:38:320
6985993332,0cyclictest248850irq/16-enp2s0f010:08:230
6985993332,0cyclictest248850irq/16-enp2s0f010:05:010
6985993332,0cyclictest248850irq/16-enp2s0f009:58:250
6985993332,0cyclictest248850irq/16-enp2s0f009:43:280
6985993332,0cyclictest248850irq/16-enp2s0f008:58:290
6985993332,0cyclictest248850irq/16-enp2s0f008:38:230
6985993332,0cyclictest248850irq/16-enp2s0f008:37:530
6985993332,0cyclictest248850irq/16-enp2s0f008:28:210
6985993332,0cyclictest248850irq/16-enp2s0f007:46:190
6985993332,0cyclictest248850irq/16-enp2s0f007:33:310
6985993332,0cyclictest248850irq/16-enp2s0f007:29:500
6985993332,0cyclictest248850irq/16-enp2s0f007:08:210
6985993332,0cyclictest168050irq/16-i91507:23:260
6985993331,1cyclictest248850irq/16-enp2s0f012:28:240
6985993331,1cyclictest248850irq/16-enp2s0f012:08:310
6985993331,1cyclictest248850irq/16-enp2s0f012:03:250
6985993331,1cyclictest248850irq/16-enp2s0f011:38:230
6985993331,1cyclictest248850irq/16-enp2s0f011:18:210
6985993331,1cyclictest248850irq/16-enp2s0f010:43:300
6985993331,1cyclictest248850irq/16-enp2s0f010:28:260
6985993331,1cyclictest248850irq/16-enp2s0f010:23:290
6985993331,1cyclictest248850irq/16-enp2s0f009:33:330
6985993331,1cyclictest248850irq/16-enp2s0f009:28:260
6985993331,1cyclictest248850irq/16-enp2s0f009:07:080
6985993331,1cyclictest248850irq/16-enp2s0f008:23:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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