You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-12-08 - 21:46

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100,+Linux+4.9.20-rt16,+x86_64 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 08, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124952620,1sleep00-21swapper/012:23:300
287532540,0sleep00-21swapper/007:50:400
147142468,8sleep00-21swapper/007:01:160
15169993533,1cyclictest248850irq/16-enp2s0f010:50:430
15169993531,0cyclictest168050irq/16-i91508:00:410
15171993433,0cyclictest168050irq/16-i91510:50:341
15171993432,1cyclictest168050irq/16-i91511:40:321
15171993432,1cyclictest168050irq/16-i91511:33:091
15171993432,1cyclictest168050irq/16-i91511:33:091
15171993432,1cyclictest168050irq/16-i91511:05:381
15171993432,1cyclictest168050irq/16-i91508:37:391
15171993432,1cyclictest168050irq/16-i91508:25:371
15171993432,1cyclictest168050irq/16-i91507:18:171
15169993432,1cyclictest248850irq/16-enp2s0f012:10:400
15169993432,1cyclictest248850irq/16-enp2s0f010:00:390
15169993432,1cyclictest248850irq/16-enp2s0f008:20:380
15169993432,1cyclictest248850irq/16-enp2s0f007:35:460
15169993432,1cyclictest248850irq/16-enp2s0f007:30:330
15169993432,1cyclictest248850irq/16-enp2s0f007:10:330
15169993432,1cyclictest248850irq/16-enp2s0f007:05:390
15171993332,0cyclictest248850irq/16-enp2s0f012:15:211
15171993332,0cyclictest248850irq/16-enp2s0f012:10:571
15171993332,0cyclictest248850irq/16-enp2s0f009:10:361
15171993332,0cyclictest248850irq/16-enp2s0f008:30:321
15171993332,0cyclictest248850irq/16-enp2s0f008:20:321
15171993332,0cyclictest248850irq/16-enp2s0f007:25:381
15171993332,0cyclictest168050irq/16-i91512:34:161
15171993332,0cyclictest168050irq/16-i91512:06:401
15171993332,0cyclictest168050irq/16-i91512:00:351
15171993332,0cyclictest168050irq/16-i91510:40:401
15171993332,0cyclictest168050irq/16-i91510:26:191
15171993332,0cyclictest168050irq/16-i91509:15:421
15171993332,0cyclictest168050irq/16-i91508:44:041
15171993332,0cyclictest168050irq/16-i91508:15:341
15171993332,0cyclictest168050irq/16-i91508:10:441
15171993332,0cyclictest168050irq/16-i91507:46:301
15171993331,1cyclictest248850irq/16-enp2s0f011:10:381
15171993331,1cyclictest248850irq/16-enp2s0f010:24:091
15171993331,1cyclictest168050irq/16-i91511:47:231
15171993331,1cyclictest168050irq/16-i91511:25:541
15171993331,1cyclictest168050irq/16-i91511:00:301
15171993331,1cyclictest168050irq/16-i91510:35:421
15171993331,1cyclictest168050irq/16-i91510:31:181
15171993331,1cyclictest168050irq/16-i91509:35:441
15171993331,1cyclictest168050irq/16-i91508:53:351
15171993331,1cyclictest168050irq/16-i91507:05:431
15169993333,0cyclictest248850irq/16-enp2s0f010:58:580
15169993332,1cyclictest248850irq/16-enp2s0f008:40:240
15169993332,1cyclictest248850irq/16-enp2s0f008:05:380
15169993332,0cyclictest248850irq/16-enp2s0f012:34:160
15169993332,0cyclictest248850irq/16-enp2s0f012:25:410
15169993332,0cyclictest248850irq/16-enp2s0f012:00:410
15169993332,0cyclictest248850irq/16-enp2s0f011:50:370
15169993332,0cyclictest248850irq/16-enp2s0f011:37:200
15169993332,0cyclictest248850irq/16-enp2s0f011:29:400
15169993332,0cyclictest248850irq/16-enp2s0f010:35:380
15169993332,0cyclictest248850irq/16-enp2s0f010:20:340
15169993332,0cyclictest248850irq/16-enp2s0f010:05:490
15169993332,0cyclictest248850irq/16-enp2s0f009:56:120
15169993332,0cyclictest248850irq/16-enp2s0f009:48:450
15169993332,0cyclictest248850irq/16-enp2s0f009:30:340
15169993332,0cyclictest248850irq/16-enp2s0f009:10:370
15169993332,0cyclictest248850irq/16-enp2s0f009:07:490
15169993332,0cyclictest248850irq/16-enp2s0f008:36:440
15169993332,0cyclictest248850irq/16-enp2s0f008:15:370
15169993332,0cyclictest248850irq/16-enp2s0f008:10:430
15169993332,0cyclictest248850irq/16-enp2s0f007:40:350
15169993332,0cyclictest248850irq/16-enp2s0f007:25:410
15169993331,1cyclictest248850irq/16-enp2s0f011:55:440
15169993331,1cyclictest248850irq/16-enp2s0f011:00:330
15169993331,1cyclictest248850irq/16-enp2s0f010:40:320
15169993331,1cyclictest248850irq/16-enp2s0f010:26:250
15169993331,1cyclictest248850irq/16-enp2s0f009:40:340
15169993331,1cyclictest248850irq/16-enp2s0f008:50:380
15169993331,1cyclictest248850irq/16-enp2s0f007:15:380
150932339,16sleep10-21swapper/107:05:101
15171993232,0cyclictest168050irq/16-i91510:10:361
15171993232,0cyclictest168050irq/16-i91509:55:311
15171993232,0cyclictest168050irq/16-i91509:40:351
15171993231,0cyclictest248850irq/16-enp2s0f009:25:361
15171993231,0cyclictest248850irq/16-enp2s0f009:22:281
15171993231,0cyclictest248850irq/16-enp2s0f007:35:411
15171993231,0cyclictest168050irq/16-i91512:25:501
15171993231,0cyclictest168050irq/16-i91511:55:451
15171993231,0cyclictest168050irq/16-i91511:54:091
15171993231,0cyclictest168050irq/16-i91511:35:341
15171993231,0cyclictest168050irq/16-i91511:15:361
15171993231,0cyclictest168050irq/16-i91510:55:371
15171993231,0cyclictest168050irq/16-i91510:45:441
15171993231,0cyclictest168050irq/16-i91510:15:201
15171993231,0cyclictest168050irq/16-i91510:05:491
15171993231,0cyclictest168050irq/16-i91510:00:371
15171993231,0cyclictest168050irq/16-i91509:30:301
15171993231,0cyclictest168050irq/16-i91509:00:471
15171993231,0cyclictest168050irq/16-i91508:55:361
15171993231,0cyclictest168050irq/16-i91508:45:201
15171993231,0cyclictest168050irq/16-i91508:05:311
15171993231,0cyclictest168050irq/16-i91507:57:541
15171993231,0cyclictest168050irq/16-i91507:43:301
15171993231,0cyclictest168050irq/16-i91507:30:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional