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2022-08-20 - 04:07

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot2.osadl.org (updated Sat Aug 20, 2022 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1482824825,11sleep10-21swapper/119:05:201
147832458,8sleep00-21swapper/019:04:520
15074993931,7cyclictest248850irq/16-enp2s0f020:12:350
15074993930,8cyclictest248850irq/16-enp2s0f022:32:360
15074993825,10cyclictest248850irq/16-enp2s0f021:31:410
15074993634,1cyclictest248850irq/16-enp2s0f022:22:360
15074993630,5cyclictest248850irq/16-enp2s0f022:52:420
15074993534,0cyclictest248850irq/16-enp2s0f020:33:550
15075993433,0cyclictest168050irq/16-i91520:29:481
15075993432,1cyclictest190450irq/16-nvkm23:37:321
15075993432,1cyclictest168050irq/16-i91522:55:111
15075993432,1cyclictest168050irq/16-i91519:57:051
15074993433,0cyclictest248850irq/16-enp2s0f020:48:390
15074993433,0cyclictest248850irq/16-enp2s0f020:37:310
15074993433,0cyclictest248850irq/16-enp2s0f020:22:350
15074993433,0cyclictest248850irq/16-enp2s0f020:07:380
15074993433,0cyclictest248850irq/16-enp2s0f019:30:400
15074993432,1cyclictest248850irq/16-enp2s0f023:58:150
15074993432,1cyclictest248850irq/16-enp2s0f023:37:350
15074993432,1cyclictest248850irq/16-enp2s0f023:27:380
15074993432,1cyclictest248850irq/16-enp2s0f023:09:450
15074993432,1cyclictest248850irq/16-enp2s0f023:02:330
15074993432,1cyclictest248850irq/16-enp2s0f023:00:360
15074993432,1cyclictest248850irq/16-enp2s0f022:27:360
15074993432,1cyclictest248850irq/16-enp2s0f022:01:060
15074993432,1cyclictest248850irq/16-enp2s0f021:42:380
15074993432,1cyclictest248850irq/16-enp2s0f020:42:360
15074993432,1cyclictest248850irq/16-enp2s0f019:52:360
15074993432,1cyclictest248850irq/16-enp2s0f019:32:330
15074993432,1cyclictest248850irq/16-enp2s0f000:32:380
15074993432,1cyclictest248850irq/16-enp2s0f000:17:550
15074993426,7cyclictest248850irq/16-enp2s0f023:47:350
15075993333,0cyclictest168050irq/16-i91520:10:291
15075993332,1cyclictest168050irq/16-i91522:21:311
15075993332,0cyclictest248850irq/16-enp2s0f022:47:381
15075993332,0cyclictest248850irq/16-enp2s0f022:27:321
15075993332,0cyclictest248850irq/16-enp2s0f020:47:351
15075993332,0cyclictest248850irq/16-enp2s0f019:07:541
15075993332,0cyclictest248850irq/16-enp2s0f019:07:541
15075993332,0cyclictest168050irq/16-i91523:48:441
15075993332,0cyclictest168050irq/16-i91523:43:331
15075993332,0cyclictest168050irq/16-i91523:15:411
15075993332,0cyclictest168050irq/16-i91522:42:301
15075993332,0cyclictest168050irq/16-i91522:37:341
15075993332,0cyclictest168050irq/16-i91522:14:471
15075993332,0cyclictest168050irq/16-i91521:47:231
15075993332,0cyclictest168050irq/16-i91520:54:151
15075993332,0cyclictest168050irq/16-i91520:32:331
15075993332,0cyclictest168050irq/16-i91520:17:341
15075993332,0cyclictest168050irq/16-i91520:13:101
15075993332,0cyclictest168050irq/16-i91520:06:541
15075993332,0cyclictest168050irq/16-i91519:57:301
15075993332,0cyclictest168050irq/16-i91519:47:381
15075993332,0cyclictest168050irq/16-i91500:03:141
15075993331,1cyclictest168050irq/16-i91522:02:311
15075993331,1cyclictest168050irq/16-i91520:42:311
15075993331,1cyclictest168050irq/16-i91519:45:391
15075993331,1cyclictest168050irq/16-i91519:17:381
15075993331,1cyclictest168050irq/16-i91519:16:571
15075993331,1cyclictest168050irq/16-i91500:23:381
15074993332,0cyclictest248850irq/16-enp2s0f023:12:390
15074993332,0cyclictest248850irq/16-enp2s0f022:38:380
15074993332,0cyclictest248850irq/16-enp2s0f022:07:330
15074993332,0cyclictest248850irq/16-enp2s0f022:02:440
15074993332,0cyclictest248850irq/16-enp2s0f021:49:380
15074993332,0cyclictest248850irq/16-enp2s0f021:22:310
15074993332,0cyclictest248850irq/16-enp2s0f021:20:410
15074993332,0cyclictest248850irq/16-enp2s0f021:13:300
15074993332,0cyclictest248850irq/16-enp2s0f021:07:180
15074993332,0cyclictest248850irq/16-enp2s0f021:02:350
15074993332,0cyclictest248850irq/16-enp2s0f020:57:250
15074993332,0cyclictest248850irq/16-enp2s0f020:52:300
15074993332,0cyclictest248850irq/16-enp2s0f019:39:360
15074993332,0cyclictest248850irq/16-enp2s0f019:17:400
15074993332,0cyclictest248850irq/16-enp2s0f019:12:350
15074993332,0cyclictest248850irq/16-enp2s0f000:28:300
15074993332,0cyclictest248850irq/16-enp2s0f000:22:300
15074993332,0cyclictest248850irq/16-enp2s0f000:12:300
15074993332,0cyclictest248850irq/16-enp2s0f000:09:300
15074993332,0cyclictest248850irq/16-enp2s0f000:02:300
15074993331,1cyclictest248850irq/16-enp2s0f023:53:330
15074993331,1cyclictest248850irq/16-enp2s0f023:24:480
15074993331,1cyclictest248850irq/16-enp2s0f023:17:340
15074993331,1cyclictest248850irq/16-enp2s0f021:54:100
15074993331,1cyclictest248850irq/16-enp2s0f021:37:530
15074993331,1cyclictest248850irq/16-enp2s0f020:02:350
15074993331,1cyclictest248850irq/16-enp2s0f019:07:300
15074993331,1cyclictest248850irq/16-enp2s0f019:07:300
15075993232,0cyclictest248850irq/16-enp2s0f022:22:331
15075993232,0cyclictest168050irq/16-i91523:21:351
15075993232,0cyclictest168050irq/16-i91522:07:381
15075993232,0cyclictest168050irq/16-i91521:22:401
15075993232,0cyclictest168050irq/16-i91521:16:461
15075993232,0cyclictest168050irq/16-i91519:38:171
15075993232,0cyclictest168050irq/16-i91500:17:401
15075993231,0cyclictest248850irq/16-enp2s0f020:57:381
15075993231,0cyclictest168050irq/16-i91523:57:361
15075993231,0cyclictest168050irq/16-i91523:52:291
15075993231,0cyclictest168050irq/16-i91523:33:401
15075993231,0cyclictest168050irq/16-i91523:22:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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