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2022-12-02 - 00:10

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 01, 2022 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1412324610,8sleep00-21swapper/019:04:460
137752418,8sleep10-21swapper/119:01:131
14248993534,0cyclictest248850irq/16-enp2s0f021:16:030
14249993432,1cyclictest168050irq/16-i91522:09:421
14249993432,1cyclictest168050irq/16-i91521:07:091
14249993432,1cyclictest168050irq/16-i91500:15:441
14248993433,0cyclictest248850irq/16-enp2s0f022:36:390
14248993432,1cyclictest248850irq/16-enp2s0f021:03:400
14248993432,1cyclictest248850irq/16-enp2s0f019:52:110
14248993432,1cyclictest248850irq/16-enp2s0f019:41:260
14248993432,1cyclictest248850irq/16-enp2s0f000:30:490
14248993432,1cyclictest248850irq/16-enp2s0f000:08:400
14248993430,0cyclictest168050irq/16-i91521:44:330
14248993430,0cyclictest168050irq/16-i91521:44:330
14249993333,0cyclictest168050irq/16-i91522:36:181
14249993332,1cyclictest168050irq/16-i91519:21:531
14249993332,0cyclictest248850irq/16-enp2s0f023:43:021
14249993332,0cyclictest248850irq/16-enp2s0f023:19:371
14249993332,0cyclictest248850irq/16-enp2s0f021:38:511
14249993332,0cyclictest168050irq/16-i91523:55:301
14249993332,0cyclictest168050irq/16-i91523:49:581
14249993332,0cyclictest168050irq/16-i91523:00:121
14249993332,0cyclictest168050irq/16-i91522:45:091
14249993332,0cyclictest168050irq/16-i91522:24:261
14249993332,0cyclictest168050irq/16-i91522:16:511
14249993332,0cyclictest168050irq/16-i91522:10:561
14249993332,0cyclictest168050irq/16-i91522:03:021
14249993332,0cyclictest168050irq/16-i91521:42:041
14249993332,0cyclictest168050irq/16-i91521:42:041
14249993332,0cyclictest168050irq/16-i91521:14:521
14249993332,0cyclictest168050irq/16-i91520:56:271
14249993332,0cyclictest168050irq/16-i91520:44:531
14249993332,0cyclictest168050irq/16-i91520:38:001
14249993332,0cyclictest168050irq/16-i91520:34:401
14249993332,0cyclictest168050irq/16-i91519:55:241
14249993332,0cyclictest168050irq/16-i91519:43:081
14249993332,0cyclictest168050irq/16-i91519:35:371
14249993332,0cyclictest168050irq/16-i91519:16:061
14249993332,0cyclictest168050irq/16-i91519:14:311
14249993332,0cyclictest168050irq/16-i91500:30:501
14249993332,0cyclictest168050irq/16-i91500:25:391
14249993332,0cyclictest168050irq/16-i91500:10:471
14249993331,1cyclictest248850irq/16-enp2s0f020:19:361
14249993331,1cyclictest168050irq/16-i91523:20:531
14249993331,1cyclictest168050irq/16-i91521:47:021
14249993331,1cyclictest168050irq/16-i91521:21:151
14249993331,1cyclictest168050irq/16-i91520:00:511
14249993331,1cyclictest168050irq/16-i91519:47:211
14249993331,1cyclictest168050irq/16-i91519:28:211
14249993331,1cyclictest168050irq/16-i91500:00:441
14248993333,0cyclictest190450irq/16-nvkm22:14:130
14248993332,1cyclictest248850irq/16-enp2s0f020:05:350
14248993332,0cyclictest248850irq/16-enp2s0f023:41:040
14248993332,0cyclictest248850irq/16-enp2s0f023:27:280
14248993332,0cyclictest248850irq/16-enp2s0f023:21:200
14248993332,0cyclictest248850irq/16-enp2s0f023:14:400
14248993332,0cyclictest248850irq/16-enp2s0f022:51:230
14248993332,0cyclictest248850irq/16-enp2s0f022:45:520
14248993332,0cyclictest248850irq/16-enp2s0f022:35:060
14248993332,0cyclictest248850irq/16-enp2s0f022:25:300
14248993332,0cyclictest248850irq/16-enp2s0f022:20:040
14248993332,0cyclictest248850irq/16-enp2s0f022:05:430
14248993332,0cyclictest248850irq/16-enp2s0f022:02:010
14248993332,0cyclictest248850irq/16-enp2s0f021:51:390
14248993332,0cyclictest248850irq/16-enp2s0f021:24:200
14248993332,0cyclictest248850irq/16-enp2s0f020:53:090
14248993332,0cyclictest248850irq/16-enp2s0f020:46:160
14248993332,0cyclictest248850irq/16-enp2s0f020:33:090
14248993332,0cyclictest248850irq/16-enp2s0f020:26:400
14248993332,0cyclictest248850irq/16-enp2s0f020:15:580
14248993332,0cyclictest248850irq/16-enp2s0f020:03:200
14248993332,0cyclictest248850irq/16-enp2s0f019:59:380
14248993332,0cyclictest248850irq/16-enp2s0f019:35:580
14248993332,0cyclictest248850irq/16-enp2s0f019:32:280
14248993332,0cyclictest248850irq/16-enp2s0f019:17:360
14248993332,0cyclictest248850irq/16-enp2s0f000:26:200
14248993332,0cyclictest248850irq/16-enp2s0f000:10:490
14248993332,0cyclictest248850irq/16-enp2s0f000:00:420
14248993332,0cyclictest168050irq/16-i91522:56:550
14248993332,0cyclictest168050irq/16-i91521:59:400
14248993332,0cyclictest168050irq/16-i91519:25:590
14248993331,1cyclictest248850irq/16-enp2s0f023:50:400
14248993331,1cyclictest248850irq/16-enp2s0f023:48:120
14248993331,1cyclictest248850irq/16-enp2s0f023:32:390
14248993331,1cyclictest248850irq/16-enp2s0f023:08:400
14248993331,1cyclictest248850irq/16-enp2s0f022:42:500
14248993331,1cyclictest248850irq/16-enp2s0f021:49:590
14248993331,1cyclictest248850irq/16-enp2s0f021:31:270
14248993331,1cyclictest248850irq/16-enp2s0f021:26:070
14248993331,1cyclictest248850irq/16-enp2s0f021:14:050
14248993331,1cyclictest248850irq/16-enp2s0f020:57:180
14248993331,1cyclictest248850irq/16-enp2s0f020:23:130
14248993331,1cyclictest248850irq/16-enp2s0f020:12:030
14248993331,1cyclictest248850irq/16-enp2s0f019:46:010
14248993331,1cyclictest248850irq/16-enp2s0f019:20:410
14248993331,1cyclictest248850irq/16-enp2s0f000:22:010
14248993331,1cyclictest168050irq/16-i91523:36:040
14248993330,0cyclictest168050irq/16-i91523:55:440
14249993232,0cyclictest168050irq/16-i91523:51:341
14249993232,0cyclictest168050irq/16-i91523:34:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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