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2025-07-14 - 21:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Mon Jul 14, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114962650,0sleep10-21swapper/109:02:421
182382570,1sleep118240-22uniq11:14:581
80902438,8sleep10-21swapper/107:00:271
8566993533,1cyclictest167950irq/16-i91511:24:541
8564993533,1cyclictest167950irq/16-i91511:54:550
8566993432,1cyclictest167950irq/16-i91511:23:211
8566993432,1cyclictest167950irq/16-i91508:40:021
8566993432,1cyclictest167950irq/16-i91507:55:201
8564993433,0cyclictest245950irq/16-enp2s0f011:27:080
8564993433,0cyclictest245950irq/16-enp2s0f009:54:300
8564993432,1cyclictest245950irq/16-enp2s0f012:31:430
8564993432,1cyclictest245950irq/16-enp2s0f012:20:380
8564993432,1cyclictest245950irq/16-enp2s0f011:45:000
8564993432,1cyclictest245950irq/16-enp2s0f011:39:550
8564993432,1cyclictest245950irq/16-enp2s0f011:30:040
8564993432,1cyclictest245950irq/16-enp2s0f010:04:560
8564993432,1cyclictest245950irq/16-enp2s0f009:55:020
8564993432,1cyclictest245950irq/16-enp2s0f009:14:560
8564993432,1cyclictest245950irq/16-enp2s0f007:35:150
8564993432,1cyclictest245950irq/16-enp2s0f007:30:030
8564993432,1cyclictest167950irq/16-i91511:05:530
81452348,18sleep00-21swapper/007:01:000
8566993332,0cyclictest245950irq/16-enp2s0f011:50:011
8566993332,0cyclictest245950irq/16-enp2s0f011:01:091
8566993332,0cyclictest245950irq/16-enp2s0f010:39:561
8566993332,0cyclictest245950irq/16-enp2s0f007:33:521
8566993332,0cyclictest167950irq/16-i91512:14:571
8566993332,0cyclictest167950irq/16-i91512:07:331
8566993332,0cyclictest167950irq/16-i91511:54:571
8566993332,0cyclictest167950irq/16-i91511:45:151
8566993332,0cyclictest167950irq/16-i91510:55:011
8566993332,0cyclictest167950irq/16-i91510:05:081
8566993332,0cyclictest167950irq/16-i91509:49:561
8566993332,0cyclictest167950irq/16-i91509:41:161
8566993332,0cyclictest167950irq/16-i91509:28:011
8566993332,0cyclictest167950irq/16-i91509:23:011
8566993332,0cyclictest167950irq/16-i91509:14:531
8566993332,0cyclictest167950irq/16-i91509:12:581
8566993332,0cyclictest167950irq/16-i91508:24:571
8566993332,0cyclictest167950irq/16-i91507:52:441
8566993332,0cyclictest167950irq/16-i91507:45:061
8566993331,1cyclictest167950irq/16-i91512:20:001
8566993331,1cyclictest167950irq/16-i91511:13:191
8566993331,1cyclictest167950irq/16-i91510:20:011
8566993331,1cyclictest167950irq/16-i91509:55:431
8566993331,1cyclictest167950irq/16-i91507:14:591
8564993333,0cyclictest245950irq/16-enp2s0f011:14:260
8564993332,0cyclictest245950irq/16-enp2s0f012:09:590
8564993332,0cyclictest245950irq/16-enp2s0f012:05:100
8564993332,0cyclictest245950irq/16-enp2s0f011:00:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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