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2022-01-26 - 12:32

Intel(R) Pentium(R) CPU 2020M @ 2.40GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Wed Jan 26, 2022 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
240132418,8sleep00-21swapper/019:08:400
239402378,8sleep10-21swapper/119:07:551
24102993631,4cyclictest242750irq/16-enp2s0f020:36:171
24102993531,0cyclictest173150irq/16-i91520:24:201
24102993433,0cyclictest242750irq/16-enp2s0f021:44:121
24102993432,1cyclictest242750irq/16-enp2s0f023:34:201
24102993432,1cyclictest242750irq/16-enp2s0f022:24:141
24102993432,1cyclictest242750irq/16-enp2s0f021:49:201
24102993432,1cyclictest242750irq/16-enp2s0f021:34:201
24102993432,1cyclictest242750irq/16-enp2s0f021:24:201
24102993432,1cyclictest242750irq/16-enp2s0f021:10:011
24102993432,1cyclictest242750irq/16-enp2s0f019:44:241
24102993432,1cyclictest242750irq/16-enp2s0f019:29:461
24102993432,1cyclictest242750irq/16-enp2s0f019:09:231
24102993432,1cyclictest242750irq/16-enp2s0f000:19:161
24102993432,1cyclictest242750irq/16-enp2s0f000:09:221
24100993433,0cyclictest173150irq/16-i91520:18:380
24100993432,2cyclictest173150irq/16-i91521:01:570
24100993432,1cyclictest173150irq/16-i91519:28:290
24102993332,0cyclictest242750irq/16-enp2s0f023:54:141
24102993332,0cyclictest242750irq/16-enp2s0f023:49:211
24102993332,0cyclictest242750irq/16-enp2s0f023:39:161
24102993332,0cyclictest242750irq/16-enp2s0f023:04:161
24102993332,0cyclictest242750irq/16-enp2s0f022:59:211
24102993332,0cyclictest242750irq/16-enp2s0f022:49:141
24102993332,0cyclictest242750irq/16-enp2s0f022:29:121
24102993332,0cyclictest242750irq/16-enp2s0f022:09:151
24102993332,0cyclictest242750irq/16-enp2s0f021:59:101
24102993332,0cyclictest242750irq/16-enp2s0f021:54:161
24102993332,0cyclictest242750irq/16-enp2s0f021:39:241
24102993332,0cyclictest242750irq/16-enp2s0f021:29:131
24102993332,0cyclictest242750irq/16-enp2s0f021:15:071
24102993332,0cyclictest242750irq/16-enp2s0f021:04:061
24102993332,0cyclictest242750irq/16-enp2s0f020:39:001
24102993332,0cyclictest242750irq/16-enp2s0f020:10:431
24102993332,0cyclictest242750irq/16-enp2s0f019:54:221
24102993332,0cyclictest242750irq/16-enp2s0f019:49:491
24102993332,0cyclictest242750irq/16-enp2s0f019:34:161
24102993332,0cyclictest242750irq/16-enp2s0f019:24:181
24102993332,0cyclictest242750irq/16-enp2s0f019:14:251
24102993332,0cyclictest242750irq/16-enp2s0f000:34:191
24102993332,0cyclictest242750irq/16-enp2s0f000:30:481
24102993332,0cyclictest242750irq/16-enp2s0f000:13:581
24102993331,1cyclictest242750irq/16-enp2s0f023:59:151
24102993331,1cyclictest242750irq/16-enp2s0f023:30:451
24102993331,1cyclictest242750irq/16-enp2s0f023:19:131
24102993331,1cyclictest242750irq/16-enp2s0f023:09:131
24102993331,1cyclictest242750irq/16-enp2s0f022:54:161
24102993331,1cyclictest242750irq/16-enp2s0f022:44:141
24102993331,1cyclictest242750irq/16-enp2s0f022:39:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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