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2024-10-04 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Thu Oct 03, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319642620,1sleep00-21swapper/009:38:280
5702590,0sleep10-21swapper/109:43:241
1887823822,8sleep00-21swapper/007:04:330
1890823712,18sleep10-21swapper/107:04:521
19285993634,1cyclictest255950irq/16-enp2s0f008:34:050
19285993534,0cyclictest255950irq/16-enp2s0f007:56:580
19286993433,0cyclictest255950irq/16-enp2s0f010:37:221
19286993433,0cyclictest255950irq/16-enp2s0f007:24:441
19286993432,1cyclictest255950irq/16-enp2s0f012:23:281
19286993432,1cyclictest255950irq/16-enp2s0f012:20:341
19286993432,1cyclictest255950irq/16-enp2s0f011:48:251
19286993432,1cyclictest168550irq/16-i91509:51:361
19286993432,1cyclictest168550irq/16-i91507:58:291
19285993433,0cyclictest255950irq/16-enp2s0f011:37:510
19285993433,0cyclictest255950irq/16-enp2s0f010:58:190
19285993433,0cyclictest255950irq/16-enp2s0f010:58:190
19285993433,0cyclictest255950irq/16-enp2s0f008:49:580
19285993432,1cyclictest255950irq/16-enp2s0f012:13:220
19285993432,1cyclictest255950irq/16-enp2s0f012:03:300
19285993432,1cyclictest255950irq/16-enp2s0f011:53:300
19285993432,1cyclictest255950irq/16-enp2s0f011:52:550
19285993432,1cyclictest255950irq/16-enp2s0f011:13:370
19285993432,1cyclictest255950irq/16-enp2s0f011:04:520
19285993432,1cyclictest255950irq/16-enp2s0f010:53:230
19285993432,1cyclictest255950irq/16-enp2s0f010:43:220
19285993432,1cyclictest255950irq/16-enp2s0f010:18:080
19285993432,1cyclictest255950irq/16-enp2s0f009:53:230
19285993432,1cyclictest255950irq/16-enp2s0f009:28:250
19285993432,1cyclictest255950irq/16-enp2s0f009:04:340
19285993432,1cyclictest255950irq/16-enp2s0f008:58:310
19285993432,1cyclictest255950irq/16-enp2s0f008:38:250
19285993432,1cyclictest255950irq/16-enp2s0f008:08:280
19285993432,1cyclictest255950irq/16-enp2s0f008:03:250
19285993432,1cyclictest255950irq/16-enp2s0f007:33:260
19285993432,1cyclictest255950irq/16-enp2s0f007:15:170
19285993432,1cyclictest255950irq/16-enp2s0f007:12:210
19285993431,2cyclictest255950irq/16-enp2s0f012:23:290
19286993333,0cyclictest168550irq/16-i91510:50:171
19286993332,1cyclictest168550irq/16-i91509:33:241
19286993332,0cyclictest255950irq/16-enp2s0f011:13:371
19286993332,0cyclictest255950irq/16-enp2s0f008:16:341
19286993332,0cyclictest168550irq/16-i91512:13:151
19286993332,0cyclictest168550irq/16-i91511:42:201
19286993332,0cyclictest168550irq/16-i91511:33:291
19286993332,0cyclictest168550irq/16-i91511:22:471
19286993332,0cyclictest168550irq/16-i91511:05:451
19286993332,0cyclictest168550irq/16-i91510:39:181
19286993332,0cyclictest168550irq/16-i91510:29:231
19286993332,0cyclictest168550irq/16-i91509:18:241
19286993332,0cyclictest168550irq/16-i91508:58:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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