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2023-10-01 - 01:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sat Sep 30, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
326282660,1sleep081ktimersoftd/010:35:280
3271526155,2sleep10-21swapper/106:56:051
5882468,8sleep00-21swapper/006:59:330
682993730,6cyclictest248850irq/16-enp2s0f008:45:190
683993534,0cyclictest168050irq/16-i91508:07:451
683993434,0cyclictest168050irq/16-i91507:42:131
683993432,1cyclictest248850irq/16-enp2s0f010:38:401
683993432,1cyclictest168050irq/16-i91510:55:131
683993432,1cyclictest168050irq/16-i91510:08:561
682993433,0cyclictest248850irq/16-enp2s0f011:05:140
682993433,0cyclictest248850irq/16-enp2s0f008:44:350
682993432,1cyclictest248850irq/16-enp2s0f012:20:170
682993432,1cyclictest248850irq/16-enp2s0f012:10:170
682993432,1cyclictest248850irq/16-enp2s0f011:41:300
682993432,1cyclictest248850irq/16-enp2s0f009:35:190
682993432,1cyclictest248850irq/16-enp2s0f007:20:030
683993332,0cyclictest248850irq/16-enp2s0f011:48:251
683993332,0cyclictest248850irq/16-enp2s0f010:30:151
683993332,0cyclictest248850irq/16-enp2s0f010:26:491
683993332,0cyclictest248850irq/16-enp2s0f007:21:111
683993332,0cyclictest248850irq/16-enp2s0f007:18:351
683993332,0cyclictest168050irq/16-i91512:20:151
683993332,0cyclictest168050irq/16-i91512:03:521
683993332,0cyclictest168050irq/16-i91511:50:261
683993332,0cyclictest168050irq/16-i91511:04:101
683993332,0cyclictest168050irq/16-i91510:54:461
683993332,0cyclictest168050irq/16-i91510:41:441
683993332,0cyclictest168050irq/16-i91509:50:161
683993332,0cyclictest168050irq/16-i91509:39:341
683993332,0cyclictest168050irq/16-i91509:24:101
683993332,0cyclictest168050irq/16-i91509:11:431
683993332,0cyclictest168050irq/16-i91509:00:151
683993332,0cyclictest168050irq/16-i91508:30:421
683993332,0cyclictest168050irq/16-i91508:21:301
683993332,0cyclictest168050irq/16-i91507:27:551
683993332,0cyclictest168050irq/16-i91507:10:181
683993332,0cyclictest168050irq/16-i91507:02:211
683993331,1cyclictest248850irq/16-enp2s0f008:55:411
683993331,1cyclictest248850irq/16-enp2s0f008:47:001
683993331,1cyclictest190450irq/16-nvkm11:25:121
683993331,1cyclictest168050irq/16-i91512:25:131
683993331,1cyclictest168050irq/16-i91512:05:231
683993331,1cyclictest168050irq/16-i91511:15:261
683993331,1cyclictest168050irq/16-i91510:20:291
683993331,1cyclictest168050irq/16-i91510:16:241
683993331,1cyclictest168050irq/16-i91509:31:301
683993331,1cyclictest168050irq/16-i91508:25:121
683993331,1cyclictest168050irq/16-i91508:00:181
683993331,1cyclictest168050irq/16-i91507:45:161
683993331,1cyclictest168050irq/16-i91507:07:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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