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2024-02-23 - 21:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Feb 23, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94272418,8sleep00-21swapper/007:05:560
9768993731,0cyclictest168750irq/16-i91510:23:190
9768993534,0cyclictest271250irq/16-enp2s0f012:02:430
9769993433,0cyclictest168750irq/16-i91510:37:281
9769993432,1cyclictest169650irq/16-nvkm08:19:201
9768993433,0cyclictest271250irq/16-enp2s0f011:56:280
9768993432,1cyclictest271250irq/16-enp2s0f012:32:260
9768993432,1cyclictest271250irq/16-enp2s0f012:19:110
9768993432,1cyclictest271250irq/16-enp2s0f011:39:140
9768993432,1cyclictest271250irq/16-enp2s0f011:24:100
9768993432,1cyclictest271250irq/16-enp2s0f011:04:150
9768993432,1cyclictest271250irq/16-enp2s0f010:54:110
9768993432,1cyclictest271250irq/16-enp2s0f009:34:290
9768993432,1cyclictest271250irq/16-enp2s0f008:55:420
9768993432,1cyclictest271250irq/16-enp2s0f007:54:230
9768993432,1cyclictest271250irq/16-enp2s0f007:13:500
9768993432,1cyclictest168750irq/16-i91509:31:040
9768993432,1cyclictest168750irq/16-i91507:20:380
9768993431,1cyclictest271250irq/16-enp2s0f012:04:210
9769993332,0cyclictest271250irq/16-enp2s0f011:39:331
9769993332,0cyclictest271250irq/16-enp2s0f011:19:131
9769993332,0cyclictest271250irq/16-enp2s0f010:09:121
9769993332,0cyclictest271250irq/16-enp2s0f009:14:131
9769993332,0cyclictest271250irq/16-enp2s0f008:08:301
9769993332,0cyclictest168750irq/16-i91512:36:371
9769993332,0cyclictest168750irq/16-i91512:15:451
9769993332,0cyclictest168750irq/16-i91512:08:571
9769993332,0cyclictest168750irq/16-i91511:34:181
9769993332,0cyclictest168750irq/16-i91511:10:391
9769993332,0cyclictest168750irq/16-i91510:51:101
9769993332,0cyclictest168750irq/16-i91509:36:051
9769993332,0cyclictest168750irq/16-i91509:26:031
9769993332,0cyclictest168750irq/16-i91509:06:401
9769993332,0cyclictest168750irq/16-i91508:39:171
9769993332,0cyclictest168750irq/16-i91508:34:171
9769993332,0cyclictest168750irq/16-i91508:24:201
9769993332,0cyclictest168750irq/16-i91507:44:461
9769993332,0cyclictest168750irq/16-i91507:26:171
9769993331,1cyclictest168750irq/16-i91512:26:591
9769993331,1cyclictest168750irq/16-i91509:56:391
9769993331,1cyclictest168750irq/16-i91509:49:121
9769993331,1cyclictest168750irq/16-i91508:29:161
9769993331,1cyclictest168750irq/16-i91507:54:211
9769993331,1cyclictest168750irq/16-i91507:15:121
9768993333,0cyclictest271250irq/16-enp2s0f008:35:510
9768993332,0cyclictest271250irq/16-enp2s0f012:34:120
9768993332,0cyclictest271250irq/16-enp2s0f012:24:110
9768993332,0cyclictest271250irq/16-enp2s0f012:14:390
9768993332,0cyclictest271250irq/16-enp2s0f012:09:070
9768993332,0cyclictest271250irq/16-enp2s0f011:44:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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