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2026-05-21 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Thu May 21, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167932488,8sleep00-21swapper/007:07:430
16866993433,0cyclictest168750irq/16-i91507:16:141
16866993432,1cyclictest168750irq/16-i91509:45:521
16866993432,1cyclictest168750irq/16-i91508:07:201
16864993434,0cyclictest246650irq/16-enp2s0f012:22:440
16864993433,0cyclictest168750irq/16-i91510:33:110
16864993433,0cyclictest168750irq/16-i91509:24:380
16864993432,1cyclictest246650irq/16-enp2s0f011:53:340
16864993432,1cyclictest246650irq/16-enp2s0f010:38:350
16864993432,1cyclictest246650irq/16-enp2s0f009:51:300
16864993432,1cyclictest246650irq/16-enp2s0f008:35:380
16864993431,2cyclictest246650irq/16-enp2s0f010:58:270
16866993332,0cyclictest246650irq/16-enp2s0f012:03:091
16866993332,0cyclictest246650irq/16-enp2s0f010:33:471
16866993332,0cyclictest246650irq/16-enp2s0f009:23:141
16866993332,0cyclictest246650irq/16-enp2s0f008:44:011
16866993332,0cyclictest246650irq/16-enp2s0f008:13:041
16866993332,0cyclictest168750irq/16-i91512:33:381
16866993332,0cyclictest168750irq/16-i91512:29:321
16866993332,0cyclictest168750irq/16-i91512:22:521
16866993332,0cyclictest168750irq/16-i91511:34:571
16866993332,0cyclictest168750irq/16-i91511:28:191
16866993332,0cyclictest168750irq/16-i91511:27:411
16866993332,0cyclictest168750irq/16-i91511:04:571
16866993332,0cyclictest168750irq/16-i91510:53:271
16866993332,0cyclictest168750irq/16-i91510:44:091
16866993332,0cyclictest168750irq/16-i91510:27:171
16866993332,0cyclictest168750irq/16-i91510:19:261
16866993332,0cyclictest168750irq/16-i91510:14:571
16866993332,0cyclictest168750irq/16-i91510:08:571
16866993332,0cyclictest168750irq/16-i91510:04:431
16866993332,0cyclictest168750irq/16-i91509:58:301
16866993332,0cyclictest168750irq/16-i91509:28:001
16866993332,0cyclictest168750irq/16-i91509:19:231
16866993332,0cyclictest168750irq/16-i91509:14:551
16866993332,0cyclictest168750irq/16-i91509:08:151
16866993332,0cyclictest168750irq/16-i91509:05:441
16866993332,0cyclictest168750irq/16-i91508:58:471
16866993332,0cyclictest168750irq/16-i91508:51:111
16866993332,0cyclictest168750irq/16-i91508:35:381
16866993332,0cyclictest168750irq/16-i91508:28:221
16866993332,0cyclictest168750irq/16-i91508:24:151
16866993332,0cyclictest168750irq/16-i91507:44:081
16866993332,0cyclictest168750irq/16-i91507:38:021
16866993332,0cyclictest168750irq/16-i91507:33:331
16866993331,1cyclictest246650irq/16-enp2s0f010:59:051
16866993331,1cyclictest168750irq/16-i91512:20:481
16866993331,1cyclictest168750irq/16-i91510:29:431
16866993331,1cyclictest168750irq/16-i91509:37:371
16864993332,0cyclictest246650irq/16-enp2s0f012:34:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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