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2025-11-15 - 22:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sat Nov 15, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135362428,8sleep10-21swapper/106:57:241
1446124110,23sleep00-21swapper/006:58:310
14888993533,1cyclictest245950irq/16-enp2s0f012:12:360
14888993533,1cyclictest245950irq/16-enp2s0f007:37:410
14889993433,0cyclictest245950irq/16-enp2s0f008:13:051
14889993433,0cyclictest167950irq/16-i91507:39:261
14889993432,1cyclictest167950irq/16-i91507:12:401
14888993433,0cyclictest245950irq/16-enp2s0f012:17:480
14888993433,0cyclictest245950irq/16-enp2s0f011:17:320
14888993433,0cyclictest245950irq/16-enp2s0f007:07:370
14888993432,1cyclictest245950irq/16-enp2s0f012:05:180
14888993432,1cyclictest245950irq/16-enp2s0f011:52:340
14888993432,1cyclictest245950irq/16-enp2s0f011:25:050
14888993432,1cyclictest245950irq/16-enp2s0f011:03:000
14888993432,1cyclictest245950irq/16-enp2s0f009:47:400
14888993432,1cyclictest245950irq/16-enp2s0f009:12:320
14888993432,1cyclictest245950irq/16-enp2s0f008:47:360
14888993432,1cyclictest245950irq/16-enp2s0f008:37:340
14888993432,1cyclictest245950irq/16-enp2s0f008:12:330
14888993432,1cyclictest245950irq/16-enp2s0f007:42:340
14888993432,1cyclictest245950irq/16-enp2s0f007:33:070
14888993432,1cyclictest245950irq/16-enp2s0f007:20:070
14889993332,0cyclictest245950irq/16-enp2s0f007:17:361
14889993331,1cyclictest167950irq/16-i91512:29:051
14889993331,1cyclictest167950irq/16-i91512:17:101
14889993331,1cyclictest167950irq/16-i91512:02:341
14889993331,1cyclictest167950irq/16-i91511:50:491
14889993331,1cyclictest167950irq/16-i91511:14:071
14889993331,1cyclictest167950irq/16-i91510:57:341
14889993331,1cyclictest167950irq/16-i91510:17:061
14889993331,1cyclictest167950irq/16-i91509:52:331
14889993331,1cyclictest167950irq/16-i91509:47:331
14889993331,1cyclictest167950irq/16-i91509:02:311
14889993331,1cyclictest167950irq/16-i91508:32:351
14888993333,0cyclictest245950irq/16-enp2s0f011:44:050
14888993332,0cyclictest245950irq/16-enp2s0f012:29:050
14888993332,0cyclictest245950irq/16-enp2s0f012:22:390
14888993332,0cyclictest245950irq/16-enp2s0f011:57:290
14888993332,0cyclictest245950irq/16-enp2s0f011:47:330
14888993332,0cyclictest245950irq/16-enp2s0f011:41:010
14888993332,0cyclictest245950irq/16-enp2s0f011:32:320
14888993332,0cyclictest245950irq/16-enp2s0f011:30:130
14888993332,0cyclictest245950irq/16-enp2s0f011:07:540
14888993332,0cyclictest245950irq/16-enp2s0f010:55:130
14888993332,0cyclictest245950irq/16-enp2s0f010:48:330
14888993332,0cyclictest245950irq/16-enp2s0f010:37:420
14888993332,0cyclictest245950irq/16-enp2s0f010:32:430
14888993332,0cyclictest245950irq/16-enp2s0f010:27:310
14888993332,0cyclictest245950irq/16-enp2s0f010:08:290
14888993332,0cyclictest245950irq/16-enp2s0f010:02:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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