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2023-01-30 - 06:08

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Mon Jan 30, 2023 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38552449,8sleep10-21swapper/119:01:041
39362428,8sleep00-21swapper/019:01:530
4235993732,4cyclictest248850irq/16-enp2s0f022:39:470
4235993731,5cyclictest248850irq/16-enp2s0f020:04:520
4235993626,9cyclictest248850irq/16-enp2s0f023:25:560
4235993534,0cyclictest248850irq/16-enp2s0f000:17:000
4235993533,1cyclictest248850irq/16-enp2s0f022:11:210
4236993434,0cyclictest248850irq/16-enp2s0f021:59:391
4236993433,1cyclictest168050irq/16-i91500:08:571
4236993433,0cyclictest248850irq/16-enp2s0f022:53:281
4236993432,1cyclictest248850irq/16-enp2s0f020:38:541
4236993432,1cyclictest248850irq/16-enp2s0f019:04:401
4236993432,1cyclictest168050irq/16-i91523:34:211
4236993432,1cyclictest168050irq/16-i91522:24:441
4236993432,1cyclictest168050irq/16-i91521:04:431
4236993432,1cyclictest168050irq/16-i91520:19:431
4236993432,1cyclictest168050irq/16-i91520:04:381
4236993432,1cyclictest168050irq/16-i91520:02:591
4236993432,1cyclictest168050irq/16-i91519:54:491
4236993432,1cyclictest168050irq/16-i91519:50:211
4236993432,1cyclictest168050irq/16-i91519:34:421
4236993432,1cyclictest168050irq/16-i91519:11:101
4236993432,1cyclictest168050irq/16-i91500:21:071
4236993432,1cyclictest168050irq/16-i91500:09:481
4236993432,1cyclictest168050irq/16-i91500:01:001
4235993434,0cyclictest248850irq/16-enp2s0f023:50:100
4235993434,0cyclictest248850irq/16-enp2s0f023:34:530
4235993434,0cyclictest248850irq/16-enp2s0f023:31:150
4235993434,0cyclictest248850irq/16-enp2s0f023:15:590
4235993434,0cyclictest248850irq/16-enp2s0f022:59:010
4235993434,0cyclictest248850irq/16-enp2s0f021:17:130
4235993433,1cyclictest248850irq/16-enp2s0f023:59:420
4235993433,0cyclictest248850irq/16-enp2s0f023:05:530
4235993433,0cyclictest248850irq/16-enp2s0f022:31:410
4235993433,0cyclictest248850irq/16-enp2s0f020:24:460
4235993432,1cyclictest248850irq/16-enp2s0f023:09:560
4235993432,1cyclictest248850irq/16-enp2s0f022:59:410
4235993432,1cyclictest248850irq/16-enp2s0f022:34:470
4235993432,1cyclictest248850irq/16-enp2s0f022:24:280
4235993432,1cyclictest248850irq/16-enp2s0f021:59:440
4235993432,1cyclictest248850irq/16-enp2s0f021:54:470
4235993432,1cyclictest248850irq/16-enp2s0f021:49:390
4235993432,1cyclictest248850irq/16-enp2s0f021:44:390
4235993432,1cyclictest248850irq/16-enp2s0f021:29:400
4235993432,1cyclictest248850irq/16-enp2s0f021:19:450
4235993432,1cyclictest248850irq/16-enp2s0f021:09:410
4235993432,1cyclictest248850irq/16-enp2s0f021:04:430
4235993432,1cyclictest248850irq/16-enp2s0f020:44:390
4235993432,1cyclictest248850irq/16-enp2s0f020:39:440
4235993432,1cyclictest248850irq/16-enp2s0f020:34:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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