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2025-02-06 - 14:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Thu Feb 06, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73272640,1sleep07328-22kernelversion20:57:590
706224415,22sleep00-21swapper/019:06:320
63302428,8sleep10-21swapper/119:02:591
7239993534,0cyclictest245950irq/16-enp2s0f021:02:570
7239993534,0cyclictest245950irq/16-enp2s0f019:22:050
7239993534,0cyclictest245950irq/16-enp2s0f000:27:220
7239993531,0cyclictest167950irq/16-i91500:13:080
7239993530,1cyclictest167950irq/16-i91519:57:020
7239993528,6cyclictest245950irq/16-enp2s0f022:49:490
7240993434,0cyclictest167950irq/16-i91522:57:091
7240993432,1cyclictest167950irq/16-i91521:47:511
7239993434,0cyclictest245950irq/16-enp2s0f021:16:370
7239993433,0cyclictest245950irq/16-enp2s0f023:41:590
7239993433,0cyclictest245950irq/16-enp2s0f023:02:250
7239993433,0cyclictest245950irq/16-enp2s0f022:17:480
7239993433,0cyclictest245950irq/16-enp2s0f021:26:220
7239993433,0cyclictest245950irq/16-enp2s0f019:44:170
7239993432,1cyclictest245950irq/16-enp2s0f023:27:560
7239993432,1cyclictest245950irq/16-enp2s0f022:13:010
7239993432,1cyclictest245950irq/16-enp2s0f022:07:580
7239993432,1cyclictest245950irq/16-enp2s0f021:37:590
7239993432,1cyclictest245950irq/16-enp2s0f020:53:010
7239993432,1cyclictest245950irq/16-enp2s0f019:38:000
7239993431,0cyclictest167950irq/16-i91520:13:000
7239993425,7cyclictest245950irq/16-enp2s0f019:08:020
7240993333,0cyclictest245950irq/16-enp2s0f021:10:471
7240993333,0cyclictest167950irq/16-i91500:06:071
7240993332,0cyclictest245950irq/16-enp2s0f023:53:021
7240993332,0cyclictest245950irq/16-enp2s0f021:27:581
7240993332,0cyclictest245950irq/16-enp2s0f020:22:241
7240993332,0cyclictest245950irq/16-enp2s0f019:52:471
7240993332,0cyclictest245950irq/16-enp2s0f019:18:301
7240993332,0cyclictest167950irq/16-i91523:46:221
7240993332,0cyclictest167950irq/16-i91523:38:171
7240993332,0cyclictest167950irq/16-i91523:27:551
7240993332,0cyclictest167950irq/16-i91523:20:571
7240993332,0cyclictest167950irq/16-i91523:07:531
7240993332,0cyclictest167950irq/16-i91522:46:411
7240993332,0cyclictest167950irq/16-i91522:25:011
7240993332,0cyclictest167950irq/16-i91522:12:491
7240993332,0cyclictest167950irq/16-i91522:07:361
7240993332,0cyclictest167950irq/16-i91521:52:511
7240993332,0cyclictest167950irq/16-i91521:46:221
7240993332,0cyclictest167950irq/16-i91521:41:031
7240993332,0cyclictest167950irq/16-i91521:32:531
7240993332,0cyclictest167950irq/16-i91521:24:271
7240993332,0cyclictest167950irq/16-i91521:21:021
7240993332,0cyclictest167950irq/16-i91521:04:381
7240993332,0cyclictest167950irq/16-i91520:57:591
7240993332,0cyclictest167950irq/16-i91520:52:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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