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2022-06-27 - 17:07

x86 Intel T1300 @1667 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #6, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Mon Jun 27, 2022 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14502650,1sleep011-21rcuc/008:48:140
39842478,8sleep00-21swapper/007:06:140
4242994131,9cyclictest248850irq/16-enp2s0f011:58:290
4242994131,9cyclictest248850irq/16-enp2s0f007:58:310
4242994032,7cyclictest248850irq/16-enp2s0f011:03:260
4242994031,8cyclictest248850irq/16-enp2s0f008:58:260
411024016,17sleep10-21swapper/107:07:271
4242993931,7cyclictest248850irq/16-enp2s0f012:09:110
4242993831,6cyclictest248850irq/16-enp2s0f011:22:220
4242993831,6cyclictest248850irq/16-enp2s0f010:28:360
4242993831,6cyclictest248850irq/16-enp2s0f009:33:330
4242993831,6cyclictest248850irq/16-enp2s0f009:28:320
4242993831,6cyclictest248850irq/16-enp2s0f008:23:320
4242993830,7cyclictest248850irq/16-enp2s0f009:18:310
4242993732,5cyclictest248850irq/16-enp2s0f007:15:580
4242993732,4cyclictest248850irq/16-enp2s0f010:23:290
4242993732,4cyclictest248850irq/16-enp2s0f010:16:470
4242993731,5cyclictest248850irq/16-enp2s0f012:21:530
4242993731,5cyclictest248850irq/16-enp2s0f010:08:340
4242993731,5cyclictest248850irq/16-enp2s0f009:46:250
4242993731,5cyclictest248850irq/16-enp2s0f009:13:340
4242993730,6cyclictest248850irq/16-enp2s0f009:07:390
4242993729,7cyclictest248850irq/16-enp2s0f011:53:330
4243993634,1cyclictest168050irq/16-i91509:03:261
4242993632,3cyclictest248850irq/16-enp2s0f012:37:410
4242993632,3cyclictest248850irq/16-enp2s0f011:23:330
4242993632,3cyclictest248850irq/16-enp2s0f010:33:290
4242993632,3cyclictest248850irq/16-enp2s0f007:33:300
4242993631,5cyclictest248850irq/16-enp2s0f009:56:270
4242993631,4cyclictest248850irq/16-enp2s0f010:40:450
4242993631,4cyclictest248850irq/16-enp2s0f009:38:380
4242993631,4cyclictest248850irq/16-enp2s0f009:25:130
4242993631,4cyclictest248850irq/16-enp2s0f009:09:470
4242993631,4cyclictest248850irq/16-enp2s0f008:53:340
4242993631,4cyclictest248850irq/16-enp2s0f008:18:390
4242993631,4cyclictest248850irq/16-enp2s0f008:11:070
4242993630,5cyclictest248850irq/16-enp2s0f012:31:550
4242993630,5cyclictest248850irq/16-enp2s0f011:43:360
4242993630,5cyclictest248850irq/16-enp2s0f010:53:310
4242993630,5cyclictest248850irq/16-enp2s0f008:31:110
4242993630,5cyclictest248850irq/16-enp2s0f007:47:310
4242993629,6cyclictest248850irq/16-enp2s0f012:23:370
4242993629,6cyclictest248850irq/16-enp2s0f010:06:290
4242993629,6cyclictest248850irq/16-enp2s0f009:58:260
4242993629,6cyclictest248850irq/16-enp2s0f007:38:320
4242993534,0cyclictest248850irq/16-enp2s0f008:42:320
4242993532,2cyclictest248850irq/16-enp2s0f010:18:250
4242993532,2cyclictest248850irq/16-enp2s0f007:24:310
4242993531,3cyclictest248850irq/16-enp2s0f012:13:280
4242993531,3cyclictest248850irq/16-enp2s0f011:41:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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