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2024-06-22 - 06:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot3.osadl.org (updated Fri Jun 21, 2024 13:34:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,7913
"cycles":100000000,7912
"load":"idle",7911
"condition":{7910
"clock":"2200"7908
"family":"x86",7907
"vendor":"Intel",7906
"processor":{7904
"dataset":"2024-01-08T16:38:52+01:00"7902
"origin":"2024-01-08T12:43:22+01:00",7901
"timestamps":{7900
"granularity":"microseconds"7898
1209:18:267896
14,09:18:147895
24,09:18:147894
13,09:18:147893
36,09:18:147892
33,09:18:147891
22,09:18:147890
14,09:18:147889
"maxima":[7888
009:18:147885
0,09:18:147884
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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