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2023-09-28 - 14:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot3.osadl.org (updated Thu Sep 28, 2023 00:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2094026833,0sleep60-21swapper/619:06:486
2104526331,0sleep00-21swapper/019:08:180
2098526327,0sleep50-21swapper/519:07:275
2111525839,0sleep30-21swapper/319:09:173
2096525538,0sleep40-21swapper/419:07:114
1915125438,0sleep10-21swapper/119:05:151
2095425336,0sleep20-21swapper/219:07:002
2089125236,0sleep70-21swapper/719:06:107
391350,0ktimersoftd/30-21swapper/319:54:273
2156699340,0cyclictest0-21swapper/020:27:220
2156699331,0cyclictest0-21swapper/021:22:360
2156699331,0cyclictest0-21swapper/019:53:080
2156699331,0cyclictest0-21swapper/019:47:000
2156699331,0cyclictest0-21swapper/000:11:000
2156699330,0cyclictest0-21swapper/023:55:510
2156699330,0cyclictest0-21swapper/000:17:260
711320,0ktimersoftd/70-21swapper/719:39:357
551320,0ktimersoftd/50-21swapper/522:24:215
391320,0ktimersoftd/3511-21ssh22:43:523
391320,0ktimersoftd/30-21swapper/323:47:453
391320,0ktimersoftd/30-21swapper/323:36:433
391320,0ktimersoftd/30-21swapper/323:33:133
391320,0ktimersoftd/30-21swapper/323:20:323
391320,0ktimersoftd/30-21swapper/323:09:133
391320,0ktimersoftd/30-21swapper/323:01:593
391320,0ktimersoftd/30-21swapper/322:46:513
391320,0ktimersoftd/30-21swapper/322:33:083
391320,0ktimersoftd/30-21swapper/322:23:503
391320,0ktimersoftd/30-21swapper/322:17:223
391320,0ktimersoftd/30-21swapper/322:11:363
391320,0ktimersoftd/30-21swapper/322:09:313
391320,0ktimersoftd/30-21swapper/321:49:283
391320,0ktimersoftd/30-21swapper/321:40:023
391320,0ktimersoftd/30-21swapper/321:35:483
391320,0ktimersoftd/30-21swapper/321:33:233
391320,0ktimersoftd/30-21swapper/321:25:083
391320,0ktimersoftd/30-21swapper/320:58:373
391320,0ktimersoftd/30-21swapper/320:51:063
391320,0ktimersoftd/30-21swapper/320:46:003
391320,0ktimersoftd/30-21swapper/320:36:213
391320,0ktimersoftd/30-21swapper/320:27:113
391320,0ktimersoftd/30-21swapper/320:23:093
391320,0ktimersoftd/30-21swapper/320:18:103
391320,0ktimersoftd/30-21swapper/320:13:403
391320,0ktimersoftd/30-21swapper/320:13:403
391320,0ktimersoftd/30-21swapper/319:56:233
391320,0ktimersoftd/30-21swapper/319:56:233
391320,0ktimersoftd/30-21swapper/319:44:033
391320,0ktimersoftd/30-21swapper/319:35:383
391320,0ktimersoftd/30-21swapper/319:28:243
391320,0ktimersoftd/30-21swapper/319:20:173
391320,0ktimersoftd/30-21swapper/319:18:083
391320,0ktimersoftd/30-21swapper/300:36:243
391320,0ktimersoftd/30-21swapper/300:36:243
391320,0ktimersoftd/30-21swapper/300:32:283
391320,0ktimersoftd/30-21swapper/300:28:313
391320,0ktimersoftd/30-21swapper/300:16:183
391320,0ktimersoftd/30-21swapper/300:12:213
391320,0ktimersoftd/30-21swapper/300:09:233
231320,0ktimersoftd/10-21swapper/120:27:211
2158399320,0cyclictest0-21swapper/323:17:433
2156699320,0cyclictest0-21swapper/023:46:250
551310,0ktimersoftd/50-21swapper/521:45:295
391310,0ktimersoftd/30-21swapper/323:40:393
21595992423,0cyclictest54-21rcuc/500:32:285
21583992423,0cyclictest0-21swapper/321:15:313
21595992322,0cyclictest54-21rcuc/523:34:275
21583992322,0cyclictest21851-21df21:55:183
21595992221,0cyclictest54-21rcuc/522:13:355
21583992221,0cyclictest5750-21users00:00:333
21583992221,0cyclictest27517-21memory20:30:253
21595992120,0cyclictest56-21ksoftirqd/520:24:525
21595992120,0cyclictest54-21rcuc/523:15:485
21595992120,0cyclictest54-21rcuc/521:27:055
21595992120,0cyclictest54-21rcuc/500:17:265
21595992120,0cyclictest54-21rcuc/500:11:405
21583992120,0cyclictest8913-21df21:00:173
21583992120,0cyclictest23293-21users19:10:273
21583992120,0cyclictest16484-21fschecks_count22:25:173
21583992120,0cyclictest12923-21idleruntime-cro21:10:003
21583992119,0cyclictest0-21swapper/321:10:413
21595992020,0cyclictest0-21swapper/521:22:365
21595992020,0cyclictest0-21swapper/520:15:275
21595992019,0cyclictest54-21rcuc/523:55:515
21595992019,0cyclictest54-21rcuc/522:29:045
21595992019,0cyclictest54-21rcuc/520:27:215
21595992019,0cyclictest54-21rcuc/500:22:025
21583992019,0cyclictest904-21smart_sda23:55:283
21583992019,0cyclictest25957-21ssh21:24:103
21583992019,0cyclictest24170-21ssh00:22:043
21583992019,0cyclictest14532-21sed20:05:003
21583992019,0cyclictest10665-21expr22:55:153
21583992019,0cyclictest0-21swapper/323:50:183
21583992019,0cyclictest0-21swapper/323:50:183
21583992019,0cyclictest0-21swapper/323:10:513
21583992019,0cyclictest0-21swapper/319:45:323
21595991919,0cyclictest0-21swapper/523:46:245
21595991919,0cyclictest0-21swapper/522:33:075
21595991919,0cyclictest0-21swapper/519:47:005
21595991919,0cyclictest0-21swapper/519:39:365
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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