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2023-01-27 - 15:18

x86 Intel Core i7-3632QM @2200 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #6, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot3.osadl.org (updated Fri Jan 27, 2023 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3107027541,0sleep30-21swapper/307:07:493
3093726836,0sleep10-21swapper/107:05:531
3107125539,0sleep40-21swapper/407:07:494
3102925336,0sleep00-21swapper/007:07:140
3092225337,0sleep50-21swapper/507:05:425
3115625235,0sleep60-21swapper/607:09:046
2920025235,0sleep70-21swapper/707:05:037
3094825134,0sleep20-21swapper/207:06:032
551330,0ktimersoftd/522046-21ssh10:11:485
471330,0ktimersoftd/40-21swapper/410:11:484
391330,0ktimersoftd/30-21swapper/312:02:153
391330,0ktimersoftd/30-21swapper/308:08:493
391330,0ktimersoftd/30-21swapper/307:57:483
101330,0ktimersoftd/00-21swapper/011:38:250
711320,0ktimersoftd/70-21swapper/712:39:087
711320,0ktimersoftd/70-21swapper/710:01:327
711320,0ktimersoftd/70-21swapper/707:57:487
471320,0ktimersoftd/40-21swapper/408:09:034
391320,0ktimersoftd/37628-21ssh09:25:123
391320,0ktimersoftd/330254-21ssh12:32:123
391320,0ktimersoftd/325136-21ssh09:42:073
391320,0ktimersoftd/30-21swapper/312:39:083
391320,0ktimersoftd/30-21swapper/312:07:573
391320,0ktimersoftd/30-21swapper/311:45:303
391320,0ktimersoftd/30-21swapper/311:33:043
391320,0ktimersoftd/30-21swapper/311:26:453
391320,0ktimersoftd/30-21swapper/311:21:393
391320,0ktimersoftd/30-21swapper/311:16:353
391320,0ktimersoftd/30-21swapper/311:08:553
391320,0ktimersoftd/30-21swapper/311:02:593
391320,0ktimersoftd/30-21swapper/310:45:543
391320,0ktimersoftd/30-21swapper/310:21:453
391320,0ktimersoftd/30-21swapper/310:15:373
391320,0ktimersoftd/30-21swapper/310:13:003
391320,0ktimersoftd/30-21swapper/310:07:443
391320,0ktimersoftd/30-21swapper/310:01:453
391320,0ktimersoftd/30-21swapper/309:56:533
391320,0ktimersoftd/30-21swapper/309:50:073
391320,0ktimersoftd/30-21swapper/309:45:593
391320,0ktimersoftd/30-21swapper/309:34:273
391320,0ktimersoftd/30-21swapper/309:19:223
391320,0ktimersoftd/30-21swapper/308:50:383
391320,0ktimersoftd/30-21swapper/308:43:313
391320,0ktimersoftd/30-21swapper/308:27:173
391320,0ktimersoftd/30-21swapper/308:19:233
391320,0ktimersoftd/30-21swapper/307:54:113
391320,0ktimersoftd/30-21swapper/307:49:313
391320,0ktimersoftd/30-21swapper/307:16:503
231320,0ktimersoftd/10-21swapper/111:22:541
231320,0ktimersoftd/10-21swapper/108:09:041
101320,0ktimersoftd/00-21swapper/011:22:540
101320,0ktimersoftd/00-21swapper/008:09:040
391310,0ktimersoftd/30-21swapper/312:23:043
391310,0ktimersoftd/30-21swapper/310:54:233
391310,0ktimersoftd/30-21swapper/307:36:063
391310,0ktimersoftd/30-21swapper/307:10:053
101310,0ktimersoftd/031155-21ssh09:49:040
101310,0ktimersoftd/00-21swapper/011:14:330
231300,0ktimersoftd/10-21swapper/109:49:041
31616992626,0cyclictest0-21swapper/108:17:121
31616992525,0cyclictest0-21swapper/111:44:391
31616992525,0cyclictest0-21swapper/111:09:091
31616992424,0cyclictest0-21swapper/111:46:181
31616992424,0cyclictest0-21swapper/110:36:581
31616992424,0cyclictest0-21swapper/110:19:141
31616992424,0cyclictest0-21swapper/109:59:491
31616992424,0cyclictest0-21swapper/109:43:441
31616992424,0cyclictest0-21swapper/108:52:421
31616992424,0cyclictest0-21swapper/108:34:571
31616992424,0cyclictest0-21swapper/108:34:571
31616992424,0cyclictest0-21swapper/107:42:491
31616992423,0cyclictest22-21rcuc/109:50:261
31616992423,0cyclictest12-21rcu_preempt10:55:321
31616992423,0cyclictest0-21swapper/109:25:591
31616992323,0cyclictest0-21swapper/112:18:291
31616992323,0cyclictest0-21swapper/112:18:291
31616992323,0cyclictest0-21swapper/112:11:411
31616992323,0cyclictest0-21swapper/111:28:331
31616992323,0cyclictest0-21swapper/111:10:491
31616992323,0cyclictest0-21swapper/110:11:481
31616992323,0cyclictest0-21swapper/108:00:331
31616992323,0cyclictest0-21swapper/107:25:371
31616992221,0cyclictest24-21ksoftirqd/107:57:481
31616992221,0cyclictest24-21ksoftirqd/107:38:061
31616992221,0cyclictest22-21rcuc/112:31:041
31616992221,0cyclictest22-21rcuc/111:55:131
31616992221,0cyclictest0-21swapper/111:38:251
31616992121,0cyclictest24-21ksoftirqd/108:23:121
31616992120,0cyclictest24-21ksoftirqd/112:26:191
31616992120,0cyclictest24-21ksoftirqd/110:52:291
31616992120,0cyclictest231ktimersoftd/112:07:421
31616992120,0cyclictest22-21rcuc/112:39:081
31616992020,0cyclictest22-21rcuc/110:01:321
31616992020,0cyclictest0-21swapper/109:24:271
31616992019,0cyclictest0-21swapper/108:36:241
31633991312,0cyclictest46-21rcuc/410:28:394
31633991212,0cyclictest0-21swapper/412:11:414
31633991212,0cyclictest0-21swapper/409:50:264
31633991211,0cyclictest46-21rcuc/411:38:254
31633991211,0cyclictest46-21rcuc/410:59:344
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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