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2023-11-29 - 17:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot3.osadl.org (updated Wed Nov 29, 2023 12:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242226833,0sleep70-21swapper/707:07:047
247426042,0sleep30-21swapper/307:07:493
262025942,0sleep50-21swapper/507:09:515
249925741,0sleep10-21swapper/107:08:111
192825437,0sleep40-21swapper/407:05:254
231425234,0sleep20-21swapper/207:05:312
254825134,0sleep00-21swapper/007:08:500
235625134,0sleep60-21swapper/607:06:076
471340,0ktimersoftd/40-21swapper/411:16:174
711330,0ktimersoftd/728898-21smart_sda12:20:297
711330,0ktimersoftd/70-21swapper/711:16:177
711330,0ktimersoftd/70-21swapper/710:15:117
711330,0ktimersoftd/70-21swapper/709:29:287
631330,0ktimersoftd/60-21swapper/612:20:296
631330,0ktimersoftd/60-21swapper/612:05:546
631330,0ktimersoftd/60-21swapper/610:05:156
631330,0ktimersoftd/60-21swapper/609:29:286
631330,0ktimersoftd/60-21swapper/608:59:496
551330,0ktimersoftd/50-21swapper/512:12:165
551330,0ktimersoftd/50-21swapper/511:16:185
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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