You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-01 - 14:38

x86 Intel Core i7-3632QM @2200 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #6, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot3.osadl.org (updated Thu Jun 01, 2023 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1134126732,0sleep20-21swapper/207:06:262
1148325943,0sleep30-21swapper/307:08:283
1129025833,0sleep70-21swapper/707:05:447
1127925842,0sleep50-21swapper/507:05:345
1138125741,0sleep40-21swapper/407:07:014
1146325538,0sleep10-21swapper/107:08:101
1125925437,0sleep60-21swapper/607:05:276
1145125134,0sleep00-21swapper/007:08:010
1181299370,0cyclictest29635-21ssh12:04:303
1181299370,0cyclictest0-21swapper/312:38:503
1181299370,0cyclictest0-21swapper/312:17:423
1181299370,0cyclictest0-21swapper/312:09:553
1181299370,0cyclictest0-21swapper/311:57:553
1181299370,0cyclictest0-21swapper/311:52:193
1181299370,0cyclictest0-21swapper/311:46:463
1181299370,0cyclictest0-21swapper/311:42:333
1181299370,0cyclictest0-21swapper/311:38:153
1181299370,0cyclictest0-21swapper/311:25:313
1181299370,0cyclictest0-21swapper/311:13:323
1181299370,0cyclictest0-21swapper/310:34:243
1181299370,0cyclictest0-21swapper/310:00:053
1181299370,0cyclictest0-21swapper/309:46:293
1181299370,0cyclictest0-21swapper/309:31:583
1181299370,0cyclictest0-21swapper/309:25:313
1181299370,0cyclictest0-21swapper/309:22:223
1181299370,0cyclictest0-21swapper/309:17:463
1181299370,0cyclictest0-21swapper/309:12:313
1181299370,0cyclictest0-21swapper/308:52:083
1181299370,0cyclictest0-21swapper/308:24:263
1181299370,0cyclictest0-21swapper/308:11:373
1181299370,0cyclictest0-21swapper/307:39:143
1181299370,0cyclictest0-21swapper/307:17:013
1181299363,0cyclictest0-21swapper/310:10:343
1181299363,0cyclictest0-21swapper/310:10:343
1181299360,0cyclictest0-21swapper/312:31:213
1181299360,0cyclictest0-21swapper/310:53:233
1181299360,0cyclictest0-21swapper/310:39:193
1181299360,0cyclictest0-21swapper/310:23:463
1181299360,0cyclictest0-21swapper/308:40:143
1181299360,0cyclictest0-21swapper/307:20:133
1181299350,0cyclictest0-21swapper/312:25:113
1181299350,0cyclictest0-21swapper/312:25:113
1181299350,0cyclictest0-21swapper/312:20:573
1181299350,0cyclictest0-21swapper/312:11:283
1181299350,0cyclictest0-21swapper/311:30:143
1181299350,0cyclictest0-21swapper/311:21:013
1181299350,0cyclictest0-21swapper/311:15:373
1181299350,0cyclictest0-21swapper/311:05:333
1181299350,0cyclictest0-21swapper/311:00:053
1181299350,0cyclictest0-21swapper/310:55:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional