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2024-07-21 - 21:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot3.osadl.org (updated Sun Jul 21, 2024 13:34:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,7913
"cycles":100000000,7912
"load":"idle",7911
"condition":{7910
"clock":"2200"7908
"family":"x86",7907
"vendor":"Intel",7906
"processor":{7904
"dataset":"2024-01-08T16:38:52+01:00"7902
"origin":"2024-01-08T12:43:22+01:00",7901
"timestamps":{7900
"granularity":"microseconds"7898
1211:49:217896
14,11:49:097895
24,11:49:097894
13,11:49:097893
36,11:49:097892
33,11:49:097891
22,11:49:097890
14,11:49:097889
"maxima":[7888
011:49:097885
0,11:49:097884
0,11:49:097883
0,11:49:097882
0,11:49:097881
0,11:49:097880
0,11:49:097879
0,11:49:097878
0,11:49:097877
0,11:49:097876
0,11:49:097875
0,11:49:097874
0,11:49:097873
0,11:49:097872
0,11:49:097871
0,11:49:097870
0,11:49:097869
0,11:49:097868
0,11:49:097867
0,11:49:097866
0,11:49:097865
0,11:49:097864
0,11:49:097863
0,11:49:097862
0,11:49:097861
0,11:49:097860
0,11:49:097859
0,11:49:097858
0,11:49:097857
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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