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2023-01-29 - 17:04

x86 Intel Core i7-3632QM @2200 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #6, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot3.osadl.org (updated Sun Jan 29, 2023 12:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2030926632,0sleep60-21swapper/607:06:076
2046126532,0sleep00-21swapper/007:08:170
2034425841,0sleep30-21swapper/307:06:373
2029425741,0sleep10-21swapper/107:05:541
2052525538,0sleep50-21swapper/507:09:125
1855725437,0sleep40-21swapper/407:05:084
2037025235,0sleep20-21swapper/207:07:002
2028225134,0sleep70-21swapper/707:05:447
2099999390,0cyclictest0-21swapper/410:51:394
2099999390,0cyclictest0-21swapper/409:48:274
2099999371,0cyclictest0-21swapper/412:35:174
2099999371,0cyclictest0-21swapper/412:35:174
2099999370,0cyclictest0-21swapper/412:21:534
2099999370,0cyclictest0-21swapper/411:58:224
2099999370,0cyclictest0-21swapper/411:54:544
2099999370,0cyclictest0-21swapper/411:20:194
2099999370,0cyclictest0-21swapper/411:12:364
2099999370,0cyclictest0-21swapper/411:07:454
2099999370,0cyclictest0-21swapper/410:55:164
2099999370,0cyclictest0-21swapper/410:47:064
2099999370,0cyclictest0-21swapper/409:54:214
2099999370,0cyclictest0-21swapper/409:11:404
2099999370,0cyclictest0-21swapper/408:50:084
2099999360,0cyclictest0-21swapper/412:02:464
2099999360,0cyclictest0-21swapper/411:42:274
2099999360,0cyclictest0-21swapper/411:15:034
2099999360,0cyclictest0-21swapper/410:17:424
2099999360,0cyclictest0-21swapper/410:11:114
2099999360,0cyclictest0-21swapper/410:07:024
2099999360,0cyclictest0-21swapper/409:56:254
2099999360,0cyclictest0-21swapper/409:19:464
2099999360,0cyclictest0-21swapper/408:19:214
2099999360,0cyclictest0-21swapper/408:05:234
2099999360,0cyclictest0-21swapper/408:02:194
2099999360,0cyclictest0-21swapper/407:47:484
2099999360,0cyclictest0-21swapper/407:20:424
391350,0ktimersoftd/30-21swapper/309:46:403
391350,0ktimersoftd/30-21swapper/308:54:413
2099999350,0cyclictest0-21swapper/411:27:574
2099999350,0cyclictest0-21swapper/410:42:574
2099999350,0cyclictest0-21swapper/407:19:444
551340,0ktimersoftd/50-21swapper/510:51:395
391340,0ktimersoftd/30-21swapper/312:05:353
231340,0ktimersoftd/10-21swapper/110:51:391
711330,0ktimersoftd/718510-21ssh10:52:297
631330,0ktimersoftd/60-21swapper/608:51:276
551330,0ktimersoftd/50-21swapper/512:21:545
551330,0ktimersoftd/50-21swapper/510:55:165
551330,0ktimersoftd/50-21swapper/510:47:065
551330,0ktimersoftd/50-21swapper/509:50:395
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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