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2019-06-17 - 06:47

Intel(R) Celeron(R) M processor 1.50GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the highest latencies:
System rack6slot5.osadl.org (updated Mon Jan 28, 2019 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181212930,1sleep018122-21mailstats07:40:030
54652860,1sleep05468-21turbostat.cron11:15:000
140252840,1sleep014027-21df_abs08:50:090
255282700,0sleep025530-21sed10:25:130
510799459,33cyclictest21429-21ssh11:31:520
510799449,32cyclictest6846-21ssh10:04:570
510799449,32cyclictest13774-21ssh10:11:500
510799438,7cyclictest2697-21taskset12:23:090
510799429,31cyclictest12896-21Xorg09:54:130
510799428,32cyclictest5717-21ssh12:25:470
510799428,32cyclictest20438-21ssh12:06:280
510799418,31cyclictest29298-21ssh11:40:230
510799418,30cyclictest32338-21ssh09:56:330
510799418,17cyclictest12896-21Xorg09:28:470
510799417,32cyclictest16049-21ssh09:39:100
5107994110,16cyclictest12896-21Xorg11:09:010
510799409,6cyclictest24963-21rm09:48:590
510799409,6cyclictest12896-21Xorg10:29:380
510799409,6cyclictest12896-21Xorg09:10:400
510799409,17cyclictest13-21rcuc/011:45:170
510799408,7cyclictest21816-21diskmemload10:41:330
510799408,30cyclictest101ktimersoftd/011:23:270
510799408,16cyclictest31969-21ssh12:20:020
510799407,31cyclictest12896-21Xorg12:32:450
510799407,31cyclictest12896-21Xorg10:54:540
510799399,16cyclictest17043-21ssh12:39:080
510799398,6cyclictest31966-21ssh10:32:000
510799398,6cyclictest12896-21Xorg11:54:360
510799398,6cyclictest12896-21Xorg10:17:520
510799398,6cyclictest1057-21ssh09:22:150
510799398,29cyclictest11-21rcu_preempt10:57:260
510799398,16cyclictest12896-21Xorg11:59:190
510799398,16cyclictest12896-21Xorg11:02:540
510799398,16cyclictest11132-21ssh10:09:380
510799398,15cyclictest22522-21cut09:10:110
510799397,17cyclictest12896-21Xorg11:47:460
510799397,16cyclictest12896-21Xorg09:15:590
510799388,15cyclictest12896-21Xorg12:10:510
510799388,15cyclictest12896-21Xorg12:02:380
510799388,15cyclictest12896-21Xorg11:27:150
510799388,15cyclictest12896-21Xorg10:37:090
510799388,15cyclictest12896-21Xorg09:41:200
510799387,5cyclictest12896-21Xorg09:04:000
510799387,29cyclictest12896-21Xorg08:11:130
510799387,16cyclictest4655-21snmpd08:31:130
5107993821,16cyclictest5105-21cyclictest09:32:520
5107993821,15cyclictest12896-21Xorg10:46:530
510799378,15cyclictest12896-21Xorg11:18:590
5107993711,24cyclictest12896-21Xorg08:51:220
510799367,15cyclictest12896-21Xorg08:27:410
510799367,15cyclictest12896-21Xorg08:09:450
510799367,15cyclictest12896-21Xorg07:42:280
510799367,15cyclictest12896-21Xorg07:20:230
510799357,5cyclictest12896-21Xorg07:55:230
510799329,20cyclictest5111-21munin-node07:10:160
510799327,23cyclictest12896-21Xorg07:45:560
5107993217,14cyclictest5105-21cyclictest08:41:180
5107993217,14cyclictest5105-21cyclictest08:01:010
5107993210,20cyclictest13754-21munin-node07:30:140
510799319,20cyclictest7581-21munin-node07:15:080
510799319,20cyclictest15846-21munin-node07:35:130
510799319,20cyclictest11680-21munin-node07:25:140
5107993123,6cyclictest5105-21cyclictest07:55:090
510799309,19cyclictest9532-21munin-node08:40:070
510799308,20cyclictest1207-21munin-node08:20:240
510799308,19cyclictest17744-21munin-node09:00:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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