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2025-02-06 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Thu Feb 06, 2025 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1689499102895373,4912cyclictest4936-21kworker/0:210:46:130
168949999445195,4738cyclictest29510-21kworker/0:012:22:340
168949998365249,4576cyclictest24404-21kworker/0:107:28:590
168949997695120,4644cyclictest16585-21kworker/0:109:54:150
168949997295090,4628cyclictest1785-21kworker/0:108:40:200
168949995554917,4627cyclictest16585-21kworker/0:110:02:130
168949993874735,4648cyclictest1785-21kworker/0:109:26:300
168949993634831,4528cyclictest1785-21kworker/0:108:59:110
168949993364814,4511cyclictest4936-21kworker/0:210:59:180
168949993074802,4494cyclictest24404-21kworker/0:107:40:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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