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2026-06-09 - 01:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Jun 08, 2026 12:45:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65579997735107,4662cyclictest12787-21kworker/0:207:47:470
65579997435087,4645cyclictest31214-21kworker/0:108:24:400
65579997355088,4643cyclictest12787-21kworker/0:207:52:540
65579993985031,4364cyclictest22728-21kworker/0:007:12:590
65579990334647,4376cyclictest31214-21kworker/0:108:46:450
65579989784620,4347cyclictest31214-21kworker/0:108:29:440
65579988714568,4299cyclictest22728-21kworker/0:007:16:080
65579986604465,4191cyclictest12787-21kworker/0:207:28:100
65579986584331,4303cyclictest1367-21kworker/0:209:43:150
65579985814274,4256cyclictest13706-21kworker/0:209:03:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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