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2021-08-04 - 21:28

Intel(R) Celeron(R) M processor 1.50GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Sep 16, 2020 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2383699111345903,5228cyclictest11979-21kworker/0:110:53:380
2383699107235601,5120cyclictest1360-21kworker/0:207:49:070
2383699107085603,5103cyclictest15014-21kworker/0:208:38:310
238369998105240,4563cyclictest26204-21kworker/0:107:28:050
238369997945228,4563cyclictest11881-21kworker/0:009:48:260
238369997895229,4557cyclictest21348-21kworker/0:112:16:280
238369997155199,4508cyclictest16683-21kworker/0:108:55:010
238369997155196,4512cyclictest21796-21kworker/0:008:05:270
238369996735179,4487cyclictest25551-21kworker/0:209:27:470
238369995165096,4413cyclictest30903-21kworker/0:111:43:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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