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2023-01-30 - 06:15

x86 Intel Celeron M @1500 MHz, Linux 5.15.32-rt39 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Jan 30, 2023 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
540199115506082,5457cyclictest28443-21kworker/0:119:20:090
540199101315185,4935cyclictest28443-21kworker/0:119:34:180
54019998375249,4585cyclictest28443-21kworker/0:119:12:180
54019996015004,4586cyclictest31493-21kworker/0:100:14:000
54019994034704,4684cyclictest16059-21kworker/0:019:39:370
54019990264638,4383cyclictest2719-21kworker/0:223:08:520
54019989844633,4340cyclictest31739-21kworker/0:220:34:100
54019988124365,4404cyclictest28443-21kworker/0:119:27:170
54019987974518,4268cyclictest18823-21kworker/0:223:34:120
54019980324004,3977cyclictest31739-21kworker/0:220:39:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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