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2025-07-12 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Jul 12, 2025 00:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
891599112565913,5332cyclictest10715-21kworker/0:120:38:500
891599109075555,5342cyclictest26973-21kworker/0:123:41:180
891599108205610,5199cyclictest11741-21kworker/0:019:20:010
891599106595435,5219cyclictest26973-21kworker/0:100:08:590
891599106595297,5310cyclictest11741-21kworker/0:019:29:420
891599106105410,5196cyclictest10715-21kworker/0:121:05:100
891599103755387,4976cyclictest10715-21kworker/0:120:43:210
891599102255256,4918cyclictest24487-21kworker/0:220:28:260
89159999355257,4674cyclictest10715-21kworker/0:121:00:480
89159998375210,4622cyclictest13849-21kworker/0:223:07:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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