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2024-07-27 - 06:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Jul 27, 2024 00:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131899106475304,5329cyclictest30292-21kworker/0:220:29:300
13189997055157,4544cyclictest30292-21kworker/0:220:39:050
13189996585127,4520cyclictest28400-21kworker/0:219:24:520
13189994214821,4589cyclictest28400-21kworker/0:219:35:220
13189992514741,4499cyclictest932-21kworker/0:121:53:320
13189990434742,4296cyclictest5772-21kworker/0:020:48:020
13189990394785,4194cyclictest25231-21kworker/0:000:12:030
13189988864757,4118cyclictest15043-21kworker/0:019:47:230
13189988574432,4413cyclictest18010-21kworker/0:223:49:490
13189988314536,4290cyclictest5772-21kworker/0:020:56:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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