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2024-10-08 - 08:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Tue Oct 08, 2024 00:44:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
140249998265023,4799cyclictest31931-21kworker/0:000:18:350
140249997895209,4569cyclictest809-21kworker/0:220:30:360
140249997635100,4652cyclictest13445-21kworker/0:121:43:500
140249996825057,4614cyclictest809-21kworker/0:220:26:150
140249993384802,4526cyclictest24112-21kworker/0:019:24:430
140249993384785,4542cyclictest32281-21kworker/0:022:17:540
140249993294786,4532cyclictest21326-21kworker/0:223:06:440
140249992454754,4480cyclictest5940-21kworker/0:000:28:450
140249991094687,4411cyclictest21274-21kworker/0:021:18:080
140249990824665,4406cyclictest13445-21kworker/0:122:00:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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