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2026-01-24 - 22:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Jan 24, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2565399107345474,5255cyclictest21465-21kworker/0:011:44:310
256539998765223,4641cyclictest4549-21kworker/0:212:15:060
256539998505209,4630cyclictest30246-21kworker/0:008:52:560
256539996875128,4548cyclictest21465-21kworker/0:012:04:560
256539994745085,4328cyclictest30246-21kworker/0:008:47:010
256539993214763,4547cyclictest4882-21kworker/0:209:10:400
256539991874695,4481cyclictest10506-21kworker/0:111:22:520
256539991254763,4351cyclictest4882-21kworker/0:209:06:120
256539991004497,4587cyclictest4549-21kworker/0:212:22:090
256539990664618,4443cyclictest19439-21kworker/0:110:06:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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