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2023-10-04 - 22:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Oct 04, 2023 12:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1657999113665953,5402cyclictest22303-21kworker/0:111:31:560
1657999109635441,5507cyclictest14275-21kworker/0:009:44:340
1657999105905397,5182cyclictest28203-21kworker/0:012:14:450
1657999102865232,5040cyclictest14275-21kworker/0:008:54:160
1657999100385334,4701cyclictest7393-21kworker/0:208:08:190
165799998965356,4537cyclictest5855-21kworker/0:007:56:110
165799998185317,4498cyclictest7393-21kworker/0:208:24:150
165799998015209,4589cyclictest14275-21kworker/0:009:08:430
165799997915182,4598cyclictest22303-21kworker/0:110:30:060
165799997265149,4566cyclictest22303-21kworker/0:110:11:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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