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2025-05-23 - 10:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Fri May 23, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2082899103005387,4902cyclictest24701-21kworker/0:123:09:100
208289998015131,4659cyclictest1004-21kworker/0:122:06:570
208289997665113,4648cyclictest5788-21kworker/0:019:51:380
208289997475114,4629cyclictest31095-21kworker/0:000:12:350
208289997335089,4633cyclictest1004-21kworker/0:121:19:460
208289996475055,4581cyclictest1004-21kworker/0:121:58:580
208289996155136,4468cyclictest5788-21kworker/0:019:40:040
208289993805034,4343cyclictest5788-21kworker/0:019:20:000
208289993524806,4542cyclictest9962-21kworker/0:223:16:550
208289993204793,4515cyclictest23881-21kworker/0:123:40:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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