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2022-01-26 - 06:25

Intel(R) Celeron(R) M processor 1.50GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Jan 26, 2022 00:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151769997105242,4465cyclictest12406-21kworker/0:119:12:330
151769997045125,4569cyclictest12406-21kworker/0:119:16:200
142412579184,203sleep00-21swapper19:05:340
151769955036,467cyclictest19695-21ssh22:00:180
151769953231,90cyclictest9068-1kworker/0:1H20:21:440
151769949735,448cyclictest12-21rcu_sched22:36:380
151769948437,205cyclictest16013-21unixbench-2d21:51:150
151769947846,257cyclictest26604-21ssh23:23:500
151769947736,380cyclictest13-21rcuc/021:43:230
151769947633,429cyclictest28415-21runrttasks23:26:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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