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2024-05-26 - 17:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sun May 26, 2024 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
840599119135902,5962cyclictest13435-21kworker/0:212:22:050
840599109985791,5205cyclictest1257-21kworker/0:108:41:020
840599107265443,5269cyclictest1257-21kworker/0:107:33:320
84059999425361,4578cyclictest32287-21kworker/0:210:26:390
84059999425233,4704cyclictest26583-21kworker/0:011:01:070
84059999045208,4684cyclictest29116-21kworker/0:209:24:300
84059998575319,4535cyclictest1257-21kworker/0:108:21:420
84059998195300,4516cyclictest1257-21kworker/0:107:51:320
84059997945185,4606cyclictest1257-21kworker/0:109:05:560
84059997465264,4479cyclictest1257-21kworker/0:108:30:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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