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2019-07-17 - 01:17

Intel(R) Celeron(R) M processor 1.50GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot5.osadl.org (updated Mon Jan 28, 2019 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181212930,1sleep018122-21mailstats07:40:030
54652860,1sleep05468-21turbostat.cron11:15:000
140252840,1sleep014027-21df_abs08:50:090
255282700,0sleep025530-21sed10:25:130
510799459,33cyclictest21429-21ssh11:31:520
510799449,32cyclictest6846-21ssh10:04:570
510799449,32cyclictest13774-21ssh10:11:500
510799438,7cyclictest2697-21taskset12:23:090
510799429,31cyclictest12896-21Xorg09:54:130
510799428,32cyclictest5717-21ssh12:25:470
510799428,32cyclictest20438-21ssh12:06:280
510799418,31cyclictest29298-21ssh11:40:230
510799418,30cyclictest32338-21ssh09:56:330
510799418,17cyclictest12896-21Xorg09:28:470
510799417,32cyclictest16049-21ssh09:39:100
5107994110,16cyclictest12896-21Xorg11:09:010
510799409,6cyclictest24963-21rm09:48:590
510799409,6cyclictest12896-21Xorg10:29:380
510799409,6cyclictest12896-21Xorg09:10:400
510799409,17cyclictest13-21rcuc/011:45:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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