You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2021-05-12 - 13:10

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Wed May 12, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216929950122572,2437cyclictest2582-21devkit-power-da22:18:430
216929927831556,1224cyclictest1724-21hald20:20:390
21692991246618,626cyclictest0-21swapper22:22:440
21692991246611,633cyclictest0-21swapper21:22:560
21692991243618,623cyclictest0-21swapper23:32:040
21692991242617,623cyclictest0-21swapper21:18:350
21692991242615,625cyclictest0-21swapper23:08:070
21692991240616,622cyclictest0-21swapper19:36:260
21692991237610,625cyclictest0-21swapper21:05:310
21692991237607,628cyclictest0-21swapper00:39:230
21692991236614,620cyclictest0-21swapper23:20:500
21692991236611,623cyclictest0-21swapper22:52:120
21692991236606,628cyclictest0-21swapper21:01:100
21692991235610,623cyclictest0-21swapper19:54:310
21692991235606,627cyclictest0-21swapper21:29:080
21692991231603,626cyclictest0-21swapper19:10:280
21692991229607,620cyclictest0-21swapper19:58:320
21692991229604,623cyclictest0-21swapper19:16:000
21692991227605,620cyclictest0-21swapper00:01:320
21692991227601,624cyclictest0-21swapper22:01:380
21692991221595,624cyclictest0-21swapper21:32:390
21692991217590,625cyclictest0-21swapper20:36:130
21692991216592,622cyclictest0-21swapper21:43:120
21692991215592,621cyclictest0-21swapper19:29:340
21692991215580,633cyclictest0-21swapper00:30:000
21692991214592,620cyclictest0-21swapper20:04:040
21692991212587,623cyclictest0-21swapper20:33:220
21692991211586,623cyclictest0-21swapper23:12:180
21692991211582,627cyclictest0-21swapper00:11:450
21692991209582,625cyclictest0-21swapper00:26:290
21692991207581,624cyclictest0-21swapper20:18:280
21692991206584,620cyclictest0-21swapper20:46:560
21692991205583,620cyclictest0-21swapper22:32:370
21692991200575,623cyclictest0-21swapper22:08:400
21692991199572,625cyclictest0-21swapper23:28:230
21692991199572,625cyclictest0-21swapper23:01:150
21692991197576,619cyclictest0-21swapper00:16:360
21692991189563,624cyclictest0-21swapper21:12:230
21692991189556,631cyclictest0-21swapper23:54:400
21692991188559,627cyclictest0-21swapper20:08:450
21692991185560,623cyclictest0-21swapper23:41:060
21692991173548,623cyclictest0-21swapper19:32:250
21692991166531,633cyclictest0-21swapper20:28:210
21692991164535,627cyclictest0-21swapper20:10:160
21692991163540,621cyclictest0-21swapper20:50:270
21692991157533,622cyclictest0-21swapper20:59:100
21692991151552,597cyclictest0-21swapper22:36:580
21692991147520,625cyclictest0-21swapper22:29:460
21692991139512,625cyclictest0-21swapper23:56:010
21692991135504,629cyclictest0-21swapper23:49:190
21692991133504,627cyclictest0-21swapper00:06:240
21692991131503,626cyclictest0-21swapper21:58:170
21692991130507,621cyclictest0-21swapper21:51:050
21692991117492,623cyclictest0-21swapper19:41:170
21692991117490,625cyclictest0-21swapper19:21:210
21692991110621,487cyclictest6525-21ssh21:47:030
21692991088610,476cyclictest19766-21ssh22:40:290
21692991022577,442cyclictest18830-21ssh23:18:100
2169299998565,431cyclictest26613-21ssh22:49:310
2169299998563,432cyclictest28865-21ssh22:13:510
2169299912523,386cyclictest7643-21ssh00:20:380
2169299836584,249cyclictest30305-21sh21:37:010
2169299825579,244cyclictest3942-21ssh23:38:560
2169299781456,322cyclictest32685-21ssh22:55:430
2169299733534,196cyclictest4532-21memory19:45:180
2169299627620,6cyclictest0-21swapper20:42:250
2152227153,13sleep00-21swapper19:09:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional