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2022-06-27 - 04:07

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Mon Jun 27, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239029953622707,2652cyclictest1724-21hald21:47:160
23902991249622,626cyclictest0-21swapper23:31:360
23902991249621,626cyclictest0-21swapper21:26:500
23902991247619,626cyclictest0-21swapper00:30:020
23902991244618,624cyclictest0-21swapper21:54:480
23902991243618,623cyclictest0-21swapper20:33:240
23902991242616,624cyclictest0-21swapper22:36:400
23902991241611,628cyclictest0-21swapper19:20:130
23902991239611,626cyclictest0-21swapper22:59:260
23902991238614,622cyclictest0-21swapper19:52:020
23902991236607,627cyclictest0-21swapper22:02:200
23902991235614,619cyclictest0-21swapper21:55:480
23902991235613,620cyclictest0-21swapper19:15:020
23902991234610,622cyclictest0-21swapper19:27:250
23902991229610,617cyclictest0-21swapper19:33:170
23902991229607,620cyclictest0-21swapper21:31:210
23902991227601,624cyclictest0-21swapper23:01:570
23902991226600,624cyclictest0-21swapper20:25:020
23902991224603,619cyclictest0-21swapper20:24:320
23902991221595,624cyclictest0-21swapper19:12:110
23902991220595,623cyclictest0-21swapper22:14:530
23902991215584,629cyclictest0-21swapper20:52:200
23902991214592,620cyclictest0-21swapper20:47:480
23902991214588,624cyclictest0-21swapper23:37:170
23902991214583,629cyclictest0-21swapper22:25:570
23902991212590,620cyclictest0-21swapper00:04:550
23902991211591,618cyclictest0-21swapper22:05:510
23902991207576,629cyclictest0-21swapper00:05:550
23902991203578,623cyclictest0-21swapper23:25:140
23902991203575,626cyclictest0-21swapper20:08:470
23902991199572,625cyclictest0-21swapper20:57:210
23902991196571,623cyclictest0-21swapper20:17:400
23902991194566,626cyclictest0-21swapper22:54:150
23902991189567,620cyclictest0-21swapper00:39:350
23902991188562,624cyclictest0-21swapper19:44:300
23902991184560,622cyclictest0-21swapper22:32:590
23902991184557,625cyclictest0-21swapper21:04:230
23902991181556,623cyclictest0-21swapper19:59:140
23902991180552,626cyclictest0-21swapper21:07:240
23902991176619,554cyclictest7325-21ntp_states23:55:220
23902991176619,554cyclictest27067-21ssh00:20:500
23902991175552,621cyclictest0-21swapper23:52:010
23902991174536,636cyclictest0-21swapper23:09:590
23902991167537,628cyclictest0-21swapper22:45:020
23902991166536,628cyclictest0-21swapper23:15:110
23902991164609,552cyclictest16267-21sh22:43:120
23902991163540,621cyclictest0-21swapper20:14:590
23902991162535,625cyclictest0-21swapper20:44:370
23902991162526,634cyclictest0-21swapper20:35:150
23902991159533,624cyclictest0-21swapper00:11:070
23902991155525,628cyclictest0-21swapper23:24:030
23902991154531,621cyclictest0-21swapper19:37:380
23902991149607,539cyclictest11539-21sh21:12:360
23902991149521,626cyclictest0-21swapper21:17:570
23902991148524,622cyclictest0-21swapper22:17:140
23902991146516,628cyclictest0-21swapper21:20:280
23902991144518,624cyclictest0-21swapper00:17:290
23902991142521,619cyclictest0-21swapper19:46:310
23902991137511,624cyclictest0-21swapper23:48:100
23902991128505,621cyclictest0-21swapper20:04:560
23902991126498,626cyclictest0-21swapper23:12:300
23902991109488,619cyclictest0-21swapper21:42:440
23902991107472,633cyclictest0-21swapper22:21:350
2390299976517,456cyclictest28508-21df21:35:120
2390299884474,407cyclictest28629-21ssh23:40:380
2390299639624,14cyclictest0-21swapper00:29:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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