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2023-01-28 - 07:32

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Sat Jan 28, 2023 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3275995295352934,18cyclictest0-21swapper21:02:570
3275991256624,630cyclictest0-21swapper20:34:090
3275991254623,629cyclictest0-21swapper20:18:240
3275991253623,628cyclictest0-21swapper21:34:260
3275991252621,629cyclictest0-21swapper23:37:120
3275991246615,629cyclictest0-21swapper23:58:580
3275991242616,624cyclictest0-21swapper21:13:400
3275991242612,628cyclictest0-21swapper20:51:340
3275991240614,624cyclictest0-21swapper20:22:150
3275991239615,622cyclictest0-21swapper22:28:520
3275991238615,621cyclictest0-21swapper00:13:320
3275991238607,629cyclictest0-21swapper19:59:390
3275991236603,631cyclictest0-21swapper20:41:410
3275991235606,627cyclictest0-21swapper22:00:040
3275991233612,619cyclictest0-21swapper22:47:170
3275991233605,626cyclictest0-21swapper19:19:270
3275991231604,625cyclictest0-21swapper22:21:000
3275991230608,620cyclictest0-21swapper23:41:030
3275991227593,632cyclictest0-21swapper22:52:490
3275991225593,630cyclictest0-21swapper20:02:500
3275991223595,626cyclictest0-21swapper21:15:510
3275991222599,621cyclictest0-21swapper00:39:090
3275991222598,622cyclictest0-21swapper19:40:330
3275991216577,637cyclictest0-21swapper19:32:510
3275991213579,632cyclictest0-21swapper20:45:020
3275991210586,622cyclictest0-21swapper21:49:310
3275991206567,637cyclictest0-21swapper00:29:070
3275991204575,627cyclictest0-21swapper23:31:500
3275991195561,632cyclictest0-21swapper22:42:160
3275991191568,621cyclictest0-21swapper21:56:530
3275991190560,628cyclictest0-21swapper23:19:060
3275991187559,626cyclictest0-21swapper23:53:460
3275991184560,622cyclictest0-21swapper21:39:080
3275991183557,624cyclictest0-21swapper19:35:420
3275991180555,622cyclictest0-21swapper21:07:490
3275991177553,622cyclictest0-21swapper20:58:560
3275991170541,627cyclictest0-21swapper19:50:260
3275991170539,629cyclictest0-21swapper22:08:060
3275991166537,627cyclictest0-21swapper23:14:350
3275991165539,624cyclictest0-21swapper21:24:130
3275991163532,629cyclictest0-21swapper22:17:090
3275991162534,626cyclictest0-21swapper21:52:210
3275991155535,618cyclictest0-21swapper23:02:010
3275991155527,626cyclictest0-21swapper00:23:050
3275991153617,533cyclictest4977-21sh00:33:480
3275991149520,627cyclictest0-21swapper23:06:230
3275991144618,523cyclictest4759-21nscd23:21:570
3275991144524,618cyclictest0-21swapper20:05:510
3275991140523,615cyclictest0-21swapper22:59:310
3275991136521,613cyclictest0-21swapper00:16:330
3275991126497,627cyclictest0-21swapper19:47:460
3275991124496,626cyclictest0-21swapper21:29:250
3275991124486,636cyclictest0-21swapper19:21:380
3275991115604,508cyclictest31289-21sh22:33:430
3275991110485,623cyclictest0-21swapper20:13:330
3275991104479,623cyclictest0-21swapper00:09:010
3275991103478,623cyclictest0-21swapper23:48:250
3275991099469,628cyclictest0-21swapper19:29:400
327599950622,325cyclictest4051-21grep19:10:250
327599942608,330cyclictest9118-21irqstats00:00:180
327599918603,311cyclictest18202-21sh21:40:280
327599895494,398cyclictest12591-21ssh23:26:290
327599878486,390cyclictest3858-21ssh22:39:350
327599873582,288cyclictest12105-21ls22:10:370
327599697593,101cyclictest9376-21timerwakeupswit20:35:290
3275996498,639cyclictest0-21swapper20:26:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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