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2022-09-30 - 17:34
/usr/bin/Xorg /usr/bin/Xorg

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Fri Sep 30, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
219089945972587,2007cyclictest1724-21hald10:00:090
21908991257625,630cyclictest0-21swapper07:30:050
21908991253622,629cyclictest0-21swapper09:17:560
21908991249619,628cyclictest0-21swapper07:23:030
21908991245614,629cyclictest0-21swapper09:22:180
21908991242617,623cyclictest0-21swapper11:29:540
21908991242610,630cyclictest0-21swapper08:08:260
21908991237612,624cyclictest0-21swapper07:49:110
21908991235605,628cyclictest0-21swapper07:55:330
21908991234613,619cyclictest0-21swapper11:24:430
21908991233612,619cyclictest0-21swapper07:16:110
21908991232613,617cyclictest0-21swapper08:47:580
21908991228601,625cyclictest0-21swapper09:56:270
21908991227602,623cyclictest0-21swapper08:36:240
21908991225597,626cyclictest0-21swapper10:47:120
21908991223603,618cyclictest0-21swapper11:09:180
21908991220598,620cyclictest0-21swapper12:32:530
21908991220591,627cyclictest0-21swapper08:56:400
21908991218594,622cyclictest0-21swapper11:39:370
21908991214594,618cyclictest0-21swapper09:07:030
21908991214592,620cyclictest0-21swapper12:16:080
21908991214591,621cyclictest0-21swapper12:21:190
21908991214588,624cyclictest0-21swapper07:40:280
21908991212591,619cyclictest0-21swapper10:50:030
21908991211586,623cyclictest0-21swapper10:18:140
21908991210581,627cyclictest0-21swapper08:41:160
21908991208584,622cyclictest0-21swapper10:33:480
21908991206583,621cyclictest0-21swapper08:51:090
21908991205585,618cyclictest0-21swapper07:50:510
21908991203582,619cyclictest0-21swapper10:28:470
21908991199571,626cyclictest0-21swapper11:58:020
21908991198583,613cyclictest0-21swapper09:02:420
21908991198575,621cyclictest0-21swapper09:27:390
21908991198575,621cyclictest0-21swapper08:33:030
21908991196567,627cyclictest0-21swapper08:19:400
21908991190564,624cyclictest0-21swapper07:26:240
21908991189564,623cyclictest0-21swapper11:41:480
21908991188570,616cyclictest0-21swapper08:00:440
21908991178557,619cyclictest0-21swapper10:08:010
21908991170546,622cyclictest0-21swapper11:53:210
21908991169546,621cyclictest0-21swapper08:24:410
21908991168541,625cyclictest0-21swapper12:09:360
21908991165536,627cyclictest0-21swapper08:28:020
21908991161533,626cyclictest0-21swapper10:20:140
21908991159544,613cyclictest0-21swapper12:04:240
21908991155536,617cyclictest0-21swapper11:13:100
21908991154527,625cyclictest0-21swapper12:25:100
21908991145518,625cyclictest0-21swapper11:03:270
21908991132498,632cyclictest0-21swapper09:30:100
21908991125500,623cyclictest0-21swapper10:58:150
21908991117497,618cyclictest0-21swapper09:50:360
21908991117489,626cyclictest0-21swapper10:39:400
21908991117486,629cyclictest0-21swapper12:39:340
21908991107480,625cyclictest0-21swapper07:10:500
21908991097468,627cyclictest0-21swapper10:43:310
21908991064619,442cyclictest591-21rm09:43:440
21908991035608,424cyclictest3956-21ssh09:47:350
21908991017595,419cyclictest22818-21sh10:12:020
2190899986583,400cyclictest29484-21ssh09:39:120
2190899984582,399cyclictest31088-21ssh11:47:390
21908999818,973cyclictest0-21swapper07:35:200
2190899979579,397cyclictest19311-21ssh11:32:050
2190899934558,373cyclictest18725-21ssh12:14:170
2190899819600,217cyclictest8906-21ssh11:19:010
2190899777577,197cyclictest7322-21df09:10:140
2190899633624,8cyclictest0-21swapper08:10:170
2039427354,13sleep00-21swapper07:05:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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