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2021-07-29 - 17:01

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Thu Jul 29, 2021 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20271991255623,630cyclictest0-21swapper08:42:370
20271991252621,629cyclictest0-21swapper09:26:200
20271991252618,632cyclictest0-21swapper10:06:410
20271991251621,628cyclictest0-21swapper07:37:280
20271991246615,629cyclictest0-21swapper07:17:230
20271991245617,626cyclictest0-21swapper12:12:480
20271991234599,632cyclictest0-21swapper11:38:280
20271991233605,626cyclictest0-21swapper10:59:070
20271991233605,626cyclictest0-21swapper10:35:300
20271991231612,617cyclictest0-21swapper08:12:080
20271991231607,622cyclictest0-21swapper08:54:110
20271991231604,625cyclictest0-21swapper11:16:110
20271991227601,624cyclictest0-21swapper10:52:250
20271991227594,631cyclictest0-21swapper12:35:540
20271991226597,627cyclictest0-21swapper09:52:270
20271991225605,618cyclictest0-21swapper08:56:310
20271991224604,618cyclictest0-21swapper10:43:320
20271991224601,621cyclictest0-21swapper11:43:290
20271991223595,626cyclictest0-21swapper07:55:240
20271991211585,624cyclictest0-21swapper10:34:390
20271991210582,626cyclictest0-21swapper09:12:560
20271991209565,642cyclictest0-21swapper11:00:270
20271991208585,621cyclictest0-21swapper07:44:300
20271991208585,621cyclictest0-21swapper07:26:050
20271991204581,621cyclictest0-21swapper08:32:240
20271991200573,625cyclictest0-21swapper12:24:210
20271991200573,625cyclictest0-21swapper08:09:280
20271991196568,626cyclictest0-21swapper07:24:050
20271991193568,623cyclictest0-21swapper09:01:020
20271991192562,628cyclictest0-21swapper10:10:020
20271991188564,622cyclictest0-21swapper09:08:350
20271991185554,629cyclictest0-21swapper09:30:310
20271991184561,621cyclictest0-21swapper09:21:380
20271991182552,628cyclictest0-21swapper08:38:260
20271991181559,620cyclictest0-21swapper10:25:570
20271991179556,621cyclictest0-21swapper07:53:330
20271991177556,619cyclictest0-21swapper12:05:460
20271991175554,619cyclictest0-21swapper08:19:000
20271991175545,628cyclictest0-21swapper12:27:520
20271991173552,619cyclictest0-21swapper09:55:280
20271991172552,618cyclictest0-21swapper08:02:460
20271991172544,626cyclictest0-21swapper07:12:510
20271991165537,626cyclictest0-21swapper11:58:140
20271991163536,625cyclictest0-21swapper11:28:550
20271991162547,613cyclictest0-21swapper12:30:430
20271991157532,623cyclictest0-21swapper11:32:260
20271991146518,626cyclictest0-21swapper08:22:410
20271991129506,621cyclictest0-21swapper07:30:360
20271991122500,620cyclictest0-21swapper10:49:040
20271991119495,622cyclictest0-21swapper08:46:480
20271991115618,495cyclictest29418-21ssh09:38:130
20271991110490,618cyclictest0-21swapper09:16:570
20271991106615,489cyclictest2928-21ssh10:23:560
20271991099477,620cyclictest0-21swapper09:40:440
20271991096475,619cyclictest0-21swapper11:47:200
20271991091469,620cyclictest0-21swapper07:45:410
20271991091468,621cyclictest0-21swapper12:01:450
20271991082459,621cyclictest0-21swapper11:08:090
20271991074452,620cyclictest0-21swapper09:49:470
20271991040578,459cyclictest17513-21munin-node11:20:230
2027199936528,405cyclictest1059-21ssh12:17:390
2027199931621,308cyclictest11463-21ssh11:50:510
2027199873596,274cyclictest19166-21cpu08:25:220
2027199814528,284cyclictest29127-21ssh10:15:440
2027199813567,244cyclictest12401-21ssh11:14:110
2027199621610,8cyclictest18111-21ssh10:03:100
2002727255,13sleep00-21swapper07:09:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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