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2021-10-22 - 01:48

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6.osadl.org (updated Thu Oct 21, 2021 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78809910917954905,54272cyclictest2582-21devkit-power-da11:50:260
7880991262628,632cyclictest0-21swapper07:37:430
7880991255624,629cyclictest0-21swapper10:03:050
7880991247620,625cyclictest0-21swapper08:31:180
7880991246614,630cyclictest0-21swapper07:49:360
7880991244615,627cyclictest0-21swapper09:56:330
7880991241613,626cyclictest0-21swapper10:38:450
7880991239612,625cyclictest0-21swapper11:23:380
7880991238615,621cyclictest0-21swapper08:38:200
7880991238612,624cyclictest0-21swapper09:33:560
7880991238611,625cyclictest0-21swapper11:17:560
7880991237607,628cyclictest0-21swapper08:46:020
7880991235601,632cyclictest0-21swapper11:03:320
7880991232604,626cyclictest0-21swapper11:41:430
7880991231612,617cyclictest0-21swapper07:53:470
7880991228603,623cyclictest0-21swapper08:43:420
7880991226596,628cyclictest0-21swapper11:39:020
7880991221601,618cyclictest0-21swapper08:50:440
7880991221598,621cyclictest0-21swapper11:32:000
7880991221597,622cyclictest0-21swapper10:18:190
7880991218590,626cyclictest0-21swapper08:04:510
7880991215588,625cyclictest0-21swapper08:28:470
7880991212586,624cyclictest0-21swapper07:23:390
7880991210586,622cyclictest0-21swapper08:19:450
7880991208583,623cyclictest0-21swapper09:17:420
7880991206588,617cyclictest0-21swapper11:07:330
7880991206571,633cyclictest0-21swapper12:37:290
7880991205579,624cyclictest0-21swapper11:45:540
7880991197576,619cyclictest0-21swapper08:09:420
7880991197570,625cyclictest0-21swapper10:29:020
7880991195569,624cyclictest0-21swapper12:20:340
7880991195566,627cyclictest0-21swapper09:12:400
7880991192576,614cyclictest0-21swapper08:23:560
7880991189619,567cyclictest24377-21ssh12:01:190
7880991187559,626cyclictest0-21swapper07:26:190
7880991186620,563cyclictest15587-21sh10:24:310
7880991186562,622cyclictest0-21swapper09:07:490
7880991182557,623cyclictest0-21swapper09:25:440
7880991182553,627cyclictest0-21swapper07:55:080
7880991175547,626cyclictest0-21swapper08:14:330
7880991174610,561cyclictest1210-21seq10:48:080
7880991174551,621cyclictest0-21swapper09:53:120
7880991174546,626cyclictest0-21swapper11:27:290
7880991171543,626cyclictest0-21swapper09:38:070
7880991169542,625cyclictest0-21swapper12:10:510
7880991165544,619cyclictest0-21swapper07:32:410
7880991164544,619cyclictest0-21swapper07:14:060
7880991161538,621cyclictest0-21swapper12:25:460
7880991161534,625cyclictest0-21swapper09:47:000
7880991160537,621cyclictest0-21swapper10:08:360
7880991160529,629cyclictest0-21swapper09:03:480
7880991156527,627cyclictest0-21swapper11:55:270
7880991152530,620cyclictest0-21swapper09:40:180
7880991151526,623cyclictest0-21swapper10:44:160
7880991136515,619cyclictest0-21swapper08:56:150
7880991136513,621cyclictest0-21swapper07:16:060
7880991132504,626cyclictest0-21swapper07:43:240
7880991128594,532cyclictest6339-21ssh10:55:100
7880991124500,622cyclictest0-21swapper12:15:030
7880991121498,621cyclictest0-21swapper12:06:300
7880991116493,621cyclictest0-21swapper09:23:530
7880991108482,624cyclictest0-21swapper10:51:590
7880991087460,625cyclictest0-21swapper10:31:030
7880991071454,615cyclictest0-21swapper12:34:380
7880991070563,504cyclictest7486-21ssh10:13:280
788099929492,434cyclictest18401-21ssh11:10:240
707827251,17sleep00-21swapper07:06:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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