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2024-05-22 - 01:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue May 21, 2024 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2813599209843105362,104476cyclictest0-21swapper09:23:130
281359910645753452,53005cyclictest0-21swapper07:13:460
281359910627053434,52836cyclictest0-21swapper07:55:080
281359910625853466,52792cyclictest0-21swapper08:35:590
281359910618653458,52728cyclictest0-21swapper07:36:020
281359910616153061,53098cyclictest0-21swapper10:04:350
281359910616053071,53087cyclictest0-21swapper08:59:560
281359910615753388,52769cyclictest0-21swapper07:43:140
281359910612953031,53096cyclictest0-21swapper11:35:010
281359910612253027,53093cyclictest0-21swapper11:04:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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