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2025-07-10 - 06:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jul 10, 2025 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
54559910754453427,54021cyclictest9873-21ssh00:03:110
54559910734653432,53791cyclictest13062-21diskmemload22:01:560
54559910703753415,53532cyclictest0-21swapper23:45:560
54559910676353400,53363cyclictest0-21swapper00:21:060
54559910675653440,53316cyclictest0-21swapper19:54:190
54559910665853381,53212cyclictest0-21swapper22:06:170
54559910658553393,53128cyclictest0-21swapper20:11:440
54559910656353442,53121cyclictest0-21swapper22:50:100
54559910655253469,53083cyclictest0-21swapper21:07:200
54559910650253428,53074cyclictest0-21swapper22:10:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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