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2024-02-22 - 05:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6.osadl.org (updated Thu Feb 22, 2024 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
116469910746753397,53974cyclictest29053-21diskmemload00:16:520
116469910672553444,53281cyclictest0-21swapper22:14:060
116469910664353386,53192cyclictest0-21swapper20:25:450
116469910655953396,53097cyclictest0-21swapper00:13:310
116469910651253388,53034cyclictest0-21swapper20:45:310
116469910648453419,53065cyclictest0-21swapper00:01:370
116469910636353461,52838cyclictest9-21ksoftirqd/019:26:380
116469910630053454,52779cyclictest0-21swapper20:51:230
116469910628353400,52817cyclictest0-21swapper20:42:200
116469910616953061,53106cyclictest0-21swapper20:54:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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