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2026-06-17 - 15:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jun 17, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1601699209931105449,104480cyclictest0-21swapper12:09:470
160169910729453474,53724cyclictest5478-21ssh10:51:040
160169910714653414,53638cyclictest777-21diskmemload11:54:530
160169910714153471,53579cyclictest7484-21kworker/u2:210:10:430
160169910713053473,53560cyclictest26991-21ssh11:23:540
160169910706453426,53546cyclictest0-21swapper11:30:460
160169910675353413,53249cyclictest0-21swapper08:35:550
160169910674353407,53245cyclictest0-21swapper08:15:400
160169910666253395,53267cyclictest0-21swapper12:23:010
160169910653653415,53121cyclictest0-21swapper07:39:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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