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2022-01-23 - 10:45

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6.osadl.org (updated Sun Jan 23, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12069991253623,628cyclictest0-21swapper20:17:400
12069991252621,629cyclictest0-21swapper21:32:410
12069991252620,630cyclictest0-21swapper22:46:120
12069991250619,629cyclictest0-21swapper00:26:210
12069991248620,626cyclictest0-21swapper00:33:530
12069991247619,626cyclictest0-21swapper21:56:480
12069991245618,625cyclictest0-21swapper20:09:470
12069991244618,624cyclictest0-21swapper00:02:340
12069991243613,628cyclictest0-21swapper00:14:080
12069991242617,623cyclictest0-21swapper21:54:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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