You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-02-17 - 15:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Feb 17, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299899910688253397,53394cyclictest32037-21kworker/0:008:33:120
299899910688053435,53323cyclictest20022-21rm10:06:090
299899910673153454,53213cyclictest133750irq/9-eth010:36:280
299899910672053437,53283cyclictest0-21swapper08:29:210
299899910667153387,53284cyclictest0-21swapper08:00:330
299899910659053444,53146cyclictest0-21swapper07:21:120
299899910657253469,53103cyclictest0-21swapper07:53:110
299899910657053387,53090cyclictest0-21swapper07:49:200
299899910651153474,53037cyclictest0-21swapper07:11:190
299899910650453462,53042cyclictest0-21swapper12:28:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional