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2023-02-06 - 19:15

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6.osadl.org (updated Mon Feb 06, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316729910598352933,53049cyclictest0-21swapper07:52:480
316729910495952874,52084cyclictest0-21swapper09:08:400
31672995293052904,23cyclictest5435-21ls12:05:410
316729945802638,1939cyclictest1724-21hald07:46:470
31672991255621,631cyclictest0-21swapper08:03:510
31672991252621,629cyclictest0-21swapper07:56:390
31672991251622,627cyclictest0-21swapper09:40:490
31672991250622,626cyclictest0-21swapper07:41:350
31672991250620,628cyclictest0-21swapper09:36:380
31672991246610,634cyclictest0-21swapper08:43:230
31672991244615,627cyclictest0-21swapper11:03:130
31672991242614,625cyclictest0-21swapper10:13:590
31672991242609,631cyclictest0-21swapper10:03:060
31672991242609,631cyclictest0-21swapper08:08:030
31672991240616,621cyclictest0-21swapper11:12:260
31672991235609,624cyclictest0-21swapper08:16:350
31672991235602,631cyclictest0-21swapper10:35:550
31672991234605,627cyclictest0-21swapper10:31:240
31672991234605,626cyclictest0-21swapper08:11:040
31672991233600,631cyclictest0-21swapper09:47:510
31672991228598,628cyclictest0-21swapper09:56:540
31672991223596,625cyclictest0-21swapper10:59:520
31672991221595,624cyclictest0-21swapper09:16:020
31672991220590,628cyclictest0-21swapper08:29:090
31672991217592,623cyclictest0-21swapper12:17:040
31672991217592,623cyclictest0-21swapper08:52:250
31672991217588,627cyclictest0-21swapper09:27:460
31672991214592,620cyclictest0-21swapper08:33:400
31672991214585,627cyclictest0-21swapper08:20:160
31672991210579,629cyclictest0-21swapper07:33:330
31672991209585,622cyclictest0-21swapper09:30:060
31672991197576,619cyclictest0-21swapper09:04:590
31672991197570,624cyclictest0-21swapper11:05:440
31672991195571,622cyclictest0-21swapper07:15:170
31672991189564,623cyclictest0-21swapper11:54:480
31672991184554,628cyclictest0-21swapper11:48:060
31672991181553,626cyclictest0-21swapper08:46:040
31672991181552,627cyclictest0-21swapper11:37:230
31672991177554,621cyclictest0-21swapper12:25:070
31672991175550,623cyclictest0-21swapper07:20:490
31672991173540,631cyclictest0-21swapper11:44:450
31672991170542,626cyclictest0-21swapper08:37:310
31672991168538,628cyclictest0-21swapper09:14:420
31672991167537,628cyclictest0-21swapper12:14:040
31672991167537,628cyclictest0-21swapper08:55:060
31672991166536,628cyclictest0-21swapper10:19:510
31672991162539,621cyclictest0-21swapper11:56:080
31672991159536,621cyclictest0-21swapper10:47:190
31672991154526,626cyclictest0-21swapper10:52:300
31672991152525,625cyclictest0-21swapper07:29:320
31672991150522,626cyclictest0-21swapper12:20:150
31672991148520,626cyclictest0-21swapper09:21:040
31672991148517,629cyclictest0-21swapper12:34:290
31672991147516,629cyclictest0-21swapper10:25:220
31672991139515,622cyclictest0-21swapper09:51:120
31672991138503,633cyclictest0-21swapper10:41:570
31672991136514,620cyclictest0-21swapper12:37:500
31672991103474,627cyclictest0-21swapper11:19:580
31672991096459,635cyclictest0-21swapper11:22:390
31672991078580,495cyclictest1348-21ssh10:09:380
31672991077454,621cyclictest0-21swapper12:02:500
3167299949621,325cyclictest483-21sshd07:10:460
3167299923510,410cyclictest10012-21ssh11:34:420
3167299913505,405cyclictest5473-21ssh11:29:210
3167299887490,394cyclictest12915-21snmpd10:24:020
31672996549,643cyclictest0-21swapper07:35:030
3090027052,14sleep00-21swapper07:06:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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