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2021-06-20 - 01:40

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6.osadl.org (updated Sat Jun 19, 2021 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1340991252623,627cyclictest0-21swapper11:21:100
1340991251622,627cyclictest0-21swapper11:53:300
1340991250620,628cyclictest0-21swapper08:19:080
1340991248621,625cyclictest0-21swapper11:29:230
1340991246620,624cyclictest0-21swapper12:39:530
1340991242618,622cyclictest0-21swapper08:30:110
1340991239616,621cyclictest0-21swapper10:15:110
1340991236611,623cyclictest0-21swapper11:40:560
1340991235610,623cyclictest0-21swapper10:34:370
1340991234610,622cyclictest0-21swapper10:12:300
1340991234610,622cyclictest0-21swapper10:01:170
1340991232612,618cyclictest0-21swapper11:08:060
1340991231605,624cyclictest0-21swapper07:18:500
1340991230604,624cyclictest0-21swapper08:53:280
1340991229598,629cyclictest0-21swapper08:59:500
1340991227605,620cyclictest0-21swapper09:04:410
1340991224601,621cyclictest0-21swapper10:54:020
1340991224596,626cyclictest0-21swapper08:12:060
1340991222599,621cyclictest0-21swapper08:27:200
1340991219593,624cyclictest0-21swapper10:41:490
1340991218593,623cyclictest0-21swapper07:13:490
1340991215589,624cyclictest0-21swapper08:21:490
1340991212583,627cyclictest0-21swapper09:32:090
1340991211590,619cyclictest0-21swapper11:31:030
1340991210585,623cyclictest0-21swapper07:23:020
1340991206587,617cyclictest0-21swapper12:33:410
1340991205576,627cyclictest0-21swapper07:58:420
1340991201566,633cyclictest0-21swapper08:44:150
1340991200574,624cyclictest0-21swapper07:36:150
1340991200573,625cyclictest0-21swapper10:29:250
1340991200572,626cyclictest0-21swapper10:36:270
1340991196564,630cyclictest0-21swapper10:55:530
1340991194567,625cyclictest0-21swapper10:46:500
1340991188560,626cyclictest0-21swapper11:14:280
1340991185554,629cyclictest0-21swapper12:23:080
1340991179554,623cyclictest0-21swapper10:22:030
1340991178551,625cyclictest0-21swapper09:36:200
1340991175560,613cyclictest0-21swapper09:07:420
1340991174548,624cyclictest0-21swapper12:15:160
1340991174548,624cyclictest0-21swapper09:17:450
1340991173552,619cyclictest0-21swapper08:05:540
1340991172548,622cyclictest0-21swapper12:14:260
1340991170553,615cyclictest0-21swapper07:27:230
1340991169546,621cyclictest0-21swapper08:47:360
1340991169542,625cyclictest0-21swapper07:41:570
1340991168545,621cyclictest0-21swapper07:30:440
1340991164537,625cyclictest0-21swapper11:45:070
1340991163536,625cyclictest0-21swapper09:47:330
1340991162530,630cyclictest0-21swapper12:04:430
1340991160533,625cyclictest0-21swapper08:37:230
1340991159533,624cyclictest0-21swapper12:08:140
1340991158529,627cyclictest0-21swapper09:12:130
1340991157528,627cyclictest0-21swapper09:55:360
1340991149525,622cyclictest0-21swapper10:06:090
1340991146527,617cyclictest0-21swapper11:19:000
1340991131508,621cyclictest0-21swapper07:47:090
1340991126498,626cyclictest0-21swapper09:20:360
1340991098475,621cyclictest0-21swapper09:27:170
134099977555,419cyclictest6752-21ssh11:01:550
134099909521,385cyclictest11500-21ssh09:42:120
134099870602,266cyclictest18082-21ssh09:50:340
134099841487,351cyclictest16614-21ssh11:59:110
134099819577,239cyclictest18451-21perl07:50:200
134099726530,193cyclictest7141-21latency_hist12:30:000
134099654594,58cyclictest2200-21ssh11:39:560
1340996448,634cyclictest0-21swapper08:04:540
3172426952,13sleep00-21swapper07:05:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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