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2022-09-25 - 12:15
/usr/bin/Xorg /usr/bin/Xorg

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6.osadl.org (updated Sun Sep 25, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26580991251622,627cyclictest0-21swapper20:53:070
26580991246619,625cyclictest0-21swapper21:28:470
26580991245619,624cyclictest0-21swapper19:28:430
26580991243618,623cyclictest0-21swapper23:51:180
26580991243617,624cyclictest0-21swapper20:34:220
26580991240611,627cyclictest0-21swapper19:42:470
26580991236611,623cyclictest0-21swapper19:54:200
26580991236609,625cyclictest0-21swapper19:36:050
26580991232608,622cyclictest0-21swapper21:19:450
26580991232603,627cyclictest0-21swapper00:05:420
26580991231612,617cyclictest0-21swapper21:53:040
26580991230600,628cyclictest0-21swapper23:18:090
26580991228601,625cyclictest0-21swapper21:31:280
26580991227602,623cyclictest0-21swapper00:26:490
26580991226605,619cyclictest0-21swapper20:39:030
26580991223596,625cyclictest0-21swapper00:35:510
26580991222599,621cyclictest0-21swapper23:41:360
26580991222596,624cyclictest0-21swapper19:12:280
26580991218590,626cyclictest0-21swapper22:57:330
26580991217593,622cyclictest0-21swapper19:17:090
26580991216593,621cyclictest0-21swapper20:13:260
26580991216588,626cyclictest0-21swapper20:17:270
26580991214592,620cyclictest0-21swapper00:13:350
26580991214591,621cyclictest0-21swapper22:26:440
26580991212591,619cyclictest0-21swapper20:09:040
26580991211583,626cyclictest0-21swapper22:13:400
26580991206584,620cyclictest0-21swapper21:35:490
26580991205584,619cyclictest0-21swapper23:38:550
26580991205576,627cyclictest0-21swapper20:55:480
26580991202578,622cyclictest0-21swapper23:04:050
26580991201574,625cyclictest0-21swapper00:33:410
26580991200578,620cyclictest0-21swapper19:34:440
26580991200573,625cyclictest0-21swapper21:24:160
26580991198576,620cyclictest0-21swapper23:07:560
26580991194565,627cyclictest0-21swapper20:23:080
26580991192566,624cyclictest0-21swapper23:58:400
26580991191569,620cyclictest0-21swapper21:00:490
26580991190567,621cyclictest0-21swapper21:09:520
26580991187559,626cyclictest0-21swapper22:31:450
26580991182557,623cyclictest0-21swapper20:25:590
26580991180555,623cyclictest0-21swapper00:04:020
26580991179551,626cyclictest0-21swapper22:38:270
26580991176554,620cyclictest0-21swapper22:43:190
26580991176553,621cyclictest0-21swapper21:44:020
26580991172547,623cyclictest0-21swapper22:02:570
26580991172544,626cyclictest0-21swapper00:19:470
26580991168538,628cyclictest0-21swapper23:33:530
26580991167550,615cyclictest0-21swapper21:12:430
26580991161539,620cyclictest0-21swapper19:23:010
26580991160542,616cyclictest0-21swapper22:46:000
26580991157533,622cyclictest0-21swapper20:00:520
26580991157531,624cyclictest0-21swapper22:06:480
26580991156532,622cyclictest0-21swapper23:46:470
26580991152529,621cyclictest0-21swapper20:44:450
26580991133512,619cyclictest0-21swapper19:59:010
26580991124496,626cyclictest0-21swapper21:45:320
26580991120494,624cyclictest0-21swapper19:46:380
26580991115487,626cyclictest0-21swapper23:26:510
26580991114500,612cyclictest0-21swapper23:10:270
26580991099593,504cyclictest14156-21ssh21:55:150
26580991091473,616cyclictest0-21swapper22:19:020
26580991086462,622cyclictest0-21swapper20:49:560
26580991029557,469cyclictest1185-21interrupts22:20:220
26580991023554,466cyclictest15471-21smart_sda23:20:390
26580991004545,456cyclictest26072-21ssh22:52:310
2658099922505,414cyclictest29885-21ssh00:21:470
2580327755,17sleep00-21swapper19:06:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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