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2022-05-26 - 21:44

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6.osadl.org (updated Fri May 20, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76469951742644,2527cyclictest1724-21hald20:40:170
76469945832430,2150cyclictest1724-21hald23:33:470
7646991258625,631cyclictest0-21swapper00:06:460
7646991254613,639cyclictest0-21swapper22:42:120
7646991241613,626cyclictest0-21swapper23:46:200
7646991241613,626cyclictest0-21swapper21:26:400
7646991239612,625cyclictest0-21swapper21:58:290
7646991239611,626cyclictest0-21swapper00:39:460
7646991233612,619cyclictest0-21swapper19:50:520
7646991230606,622cyclictest0-21swapper23:52:320
7646991221595,624cyclictest0-21swapper22:24:470
7646991221587,632cyclictest0-21swapper23:03:280
7646991217592,623cyclictest0-21swapper22:58:260
7646991217592,623cyclictest0-21swapper22:16:340
7646991215591,622cyclictest0-21swapper23:23:340
7646991213591,620cyclictest0-21swapper00:04:250
7646991212589,621cyclictest0-21swapper23:11:500
7646991207580,625cyclictest0-21swapper20:16:400
7646991207577,628cyclictest0-21swapper19:57:140
7646991207576,629cyclictest0-21swapper20:35:350
7646991206576,628cyclictest0-21swapper20:51:200
7646991205579,624cyclictest0-21swapper23:19:020
7646991203578,623cyclictest0-21swapper19:47:310
7646991203575,626cyclictest0-21swapper23:59:140
7646991202578,622cyclictest0-21swapper22:46:030
7646991201577,622cyclictest0-21swapper21:16:370
7646991201568,631cyclictest0-21swapper20:45:480
7646991190565,623cyclictest0-21swapper21:33:520
7646991190560,628cyclictest0-21swapper21:02:530
7646991188566,620cyclictest0-21swapper22:03:510
7646991187560,625cyclictest0-21swapper22:54:250
7646991185564,619cyclictest0-21swapper19:44:510
7646991181555,624cyclictest0-21swapper22:26:170
7646991181551,628cyclictest0-21swapper19:22:340
7646991180552,626cyclictest0-21swapper00:27:020
7646991177549,626cyclictest0-21swapper21:43:450
7646991171547,622cyclictest0-21swapper21:05:240
7646991171544,625cyclictest0-21swapper19:19:230
7646991167541,624cyclictest0-21swapper20:31:540
7646991164541,621cyclictest0-21swapper00:19:400
7646991163616,543cyclictest5545-21ssh22:08:220
7646991158529,627cyclictest0-21swapper19:10:310
7646991156616,537cyclictest19645-21ssh00:32:540
7646991156532,622cyclictest0-21swapper22:10:530
7646991156528,626cyclictest0-21swapper20:07:270
7646991154530,622cyclictest0-21swapper22:30:080
7646991151612,536cyclictest2093-21runrttasks21:46:360
7646991151523,626cyclictest0-21swapper19:28:160
7646991149524,623cyclictest0-21swapper20:25:420
7646991142517,623cyclictest0-21swapper21:13:560
7646991142516,624cyclictest0-21swapper00:23:310
7646991137504,631cyclictest0-21swapper20:59:420
7646991124508,614cyclictest0-21swapper22:39:410
7646991124505,617cyclictest0-21swapper20:01:250
7646991122492,628cyclictest0-21swapper21:22:090
7646991118503,613cyclictest0-21swapper23:27:250
7646991115487,626cyclictest0-21swapper19:32:570
7646991114491,621cyclictest0-21swapper19:39:190
7646991107481,624cyclictest0-21swapper20:21:010
7646991102480,620cyclictest0-21swapper23:05:590
7646991077578,497cyclictest14074-21ssh21:37:030
7646991036554,478cyclictest1713-21runrttasks20:13:090
7646991007543,461cyclictest8726-21ssh23:35:570
764699975520,452cyclictest14795-21munin-run23:45:000
764699954616,335cyclictest24128-21ssh21:50:170
764699871475,393cyclictest3901-21ssh00:12:080
558326850,14sleep00-21swapper19:05:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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