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2021-10-26 - 22:12

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6.osadl.org (updated Tue Oct 26, 2021 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322949922161327,886cyclictest2582-21devkit-power-da09:38:420
32294991262623,637cyclictest0-21swapper10:43:400
32294991251622,627cyclictest0-21swapper08:51:180
32294991249620,627cyclictest0-21swapper08:55:290
32294991245618,625cyclictest0-21swapper07:24:230
32294991244614,629cyclictest0-21swapper07:18:510
32294991243617,624cyclictest0-21swapper07:28:240
32294991243609,632cyclictest0-21swapper09:45:330
32294991241603,636cyclictest0-21swapper11:35:050
32294991236611,623cyclictest0-21swapper08:16:080
32294991234612,620cyclictest0-21swapper08:38:540
32294991233604,627cyclictest0-21swapper09:43:330
32294991229606,621cyclictest0-21swapper07:38:070
32294991228603,623cyclictest0-21swapper11:26:330
32294991228601,625cyclictest0-21swapper07:58:230
32294991227601,624cyclictest0-21swapper08:01:230
32294991227597,628cyclictest0-21swapper12:25:200
32294991226600,624cyclictest0-21swapper07:13:300
32294991226598,626cyclictest0-21swapper12:34:520
32294991225605,618cyclictest0-21swapper11:55:110
32294991221598,621cyclictest0-21swapper11:18:200
32294991220590,628cyclictest0-21swapper09:15:150
32294991218597,619cyclictest0-21swapper12:18:280
32294991217592,623cyclictest0-21swapper08:46:570
32294991216596,618cyclictest0-21swapper11:14:090
32294991216582,631cyclictest0-21swapper12:21:280
32294991214591,621cyclictest0-21swapper08:10:460
32294991213582,629cyclictest0-21swapper11:52:400
32294991212587,623cyclictest0-21swapper12:09:350
32294991210585,623cyclictest0-21swapper09:57:370
32294991209585,622cyclictest0-21swapper07:44:290
32294991208585,621cyclictest0-21swapper12:13:560
32294991207585,620cyclictest0-21swapper07:30:450
32294991207579,626cyclictest0-21swapper10:31:370
32294991204578,624cyclictest0-21swapper10:55:140
32294991203575,626cyclictest0-21swapper09:23:470
32294991203575,626cyclictest0-21swapper08:21:590
32294991201582,617cyclictest0-21swapper07:48:300
32294991196571,623cyclictest0-21swapper12:39:140
32294991196570,624cyclictest0-21swapper07:54:110
32294991189567,620cyclictest0-21swapper09:13:240
32294991185566,617cyclictest0-21swapper10:06:500
32294991182557,623cyclictest0-21swapper09:34:500
32294991180613,565cyclictest10856-21ssh10:26:550
32294991180608,569cyclictest1724-21hald10:48:120
32294991180556,622cyclictest0-21swapper10:36:080
32294991178549,627cyclictest0-21swapper10:01:080
32294991171606,562cyclictest8247-21ssh10:24:050
32294991166543,621cyclictest0-21swapper11:31:240
32294991166537,627cyclictest0-21swapper11:24:320
32294991160542,616cyclictest0-21swapper08:41:350
32294991154529,623cyclictest0-21swapper09:07:330
32294991153527,624cyclictest0-21swapper08:28:410
32294991152530,620cyclictest0-21swapper09:54:360
32294991151526,623cyclictest0-21swapper10:13:210
32294991141591,548cyclictest5485-21ssh11:45:480
32294991140516,622cyclictest0-21swapper11:07:370
32294991138515,621cyclictest0-21swapper11:02:060
32294991121511,608cyclictest0-21swapper10:19:030
32294991119495,622cyclictest0-21swapper09:28:190
32294991108485,621cyclictest0-21swapper09:04:320
32294991092465,625cyclictest0-21swapper08:32:120
32294991088464,623cyclictest0-21swapper12:00:120
32294991001519,478cyclictest3215-21taskset11:43:370
3229499949592,353cyclictest28940-21ls10:50:520
3229499634619,14cyclictest0-21swapper08:09:060
3162027154,13sleep00-21swapper07:07:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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