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2023-01-27 - 15:28

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot6.osadl.org (updated Fri Jan 27, 2023 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170689910977755013,54762cyclictest2582-21devkit-power-da12:16:360
17068991257624,631cyclictest0-21swapper09:41:010
17068991248617,629cyclictest0-21swapper07:26:420
17068991248612,634cyclictest0-21swapper10:58:530
17068991246619,625cyclictest0-21swapper12:24:380
17068991244615,627cyclictest0-21swapper08:08:340
17068991242612,628cyclictest0-21swapper08:50:060
17068991242611,629cyclictest0-21swapper07:34:540
17068991241612,627cyclictest0-21swapper08:02:320
17068991238611,625cyclictest0-21swapper07:24:310
17068991238610,626cyclictest0-21swapper07:13:580
17068991237611,624cyclictest0-21swapper09:54:450
17068991237610,625cyclictest0-21swapper11:51:280
17068991236610,624cyclictest0-21swapper08:43:440
17068991230600,628cyclictest0-21swapper09:06:010
17068991229606,621cyclictest0-21swapper10:43:390
17068991227595,630cyclictest0-21swapper11:33:230
17068991226601,623cyclictest0-21swapper09:03:300
17068991225597,626cyclictest0-21swapper08:10:050
17068991225596,627cyclictest0-21swapper10:16:310
17068991223596,625cyclictest0-21swapper11:59:510
17068991220593,625cyclictest0-21swapper12:28:290
17068991218593,623cyclictest0-21swapper11:19:590
17068991215590,623cyclictest0-21swapper07:37:050
17068991215584,629cyclictest0-21swapper07:50:090
17068991213582,628cyclictest0-21swapper08:15:560
17068991212583,627cyclictest0-21swapper12:12:040
17068991207580,625cyclictest0-21swapper11:11:370
17068991200569,629cyclictest0-21swapper08:47:050
17068991199573,624cyclictest0-21swapper09:34:490
17068991197564,630cyclictest0-21swapper10:32:560
17068991195562,631cyclictest0-21swapper10:09:290
17068991188560,626cyclictest0-21swapper12:09:230
17068991188558,628cyclictest0-21swapper07:18:000
17068991188556,630cyclictest0-21swapper08:27:400
17068991186563,621cyclictest0-21swapper10:53:420
17068991186559,625cyclictest0-21swapper08:37:120
17068991183624,557cyclictest3363-21ssh10:22:030
17068991183557,624cyclictest0-21swapper11:46:070
17068991177550,625cyclictest0-21swapper09:18:240
17068991173541,630cyclictest0-21swapper07:43:470
17068991171543,626cyclictest0-21swapper11:44:460
17068991171538,631cyclictest0-21swapper11:06:550
17068991169546,621cyclictest0-21swapper11:26:510
17068991169539,628cyclictest0-21swapper10:27:540
17068991159610,546cyclictest17710-21ssh09:24:360
17068991152518,632cyclictest0-21swapper11:24:100
17068991151606,542cyclictest18364-21ssh09:25:160
17068991145522,621cyclictest0-21swapper10:10:390
17068991140517,621cyclictest0-21swapper08:20:070
17068991135506,627cyclictest0-21swapper08:58:080
17068991134598,533cyclictest5319-21ssh09:10:120
17068991132508,622cyclictest0-21swapper10:04:070
17068991127497,628cyclictest0-21swapper09:46:520
17068991125495,628cyclictest0-21swapper07:56:510
17068991119494,623cyclictest0-21swapper12:36:410
17068991115489,624cyclictest0-21swapper10:38:170
17068991092465,625cyclictest0-21swapper12:31:200
17068991082459,621cyclictest0-21swapper11:01:340
1706899995527,465cyclictest20907-21ls08:30:300
1706899971615,353cyclictest1966-21ssh11:35:240
1706899969515,451cyclictest32612-21diskstats07:45:170
1706899922486,433cyclictest25692-21ssh10:48:200
1706899841452,387cyclictest22606-21ssh12:00:010
1706899762612,147cyclictest28464-21ssh09:36:090
1706899747603,141cyclictest14169-21ssh09:57:150
1668227254,13sleep00-21swapper07:08:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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