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2022-06-30 - 21:40

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot6.osadl.org (updated Thu Jun 30, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4704991304878,423cyclictest1724-21hald10:16:370
4704991255612,15cyclictest0-21swapper10:22:280
4704991251606,643cyclictest0-21swapper12:21:120
4704991249616,631cyclictest0-21swapper11:37:300
4704991248620,626cyclictest0-21swapper07:49:340
4704991247620,625cyclictest0-21swapper07:10:130
4704991246618,626cyclictest0-21swapper08:19:430
4704991243618,623cyclictest0-21swapper07:58:470
4704991243617,624cyclictest0-21swapper08:49:410
4704991241613,626cyclictest0-21swapper09:51:490
4704991239611,626cyclictest0-21swapper09:45:170
4704991239601,636cyclictest0-21swapper12:33:260
4704991238594,642cyclictest0-21swapper11:17:040
4704991236609,625cyclictest0-21swapper07:38:210
4704991234606,626cyclictest0-21swapper12:18:220
4704991230607,621cyclictest0-21swapper11:05:510
4704991230606,622cyclictest0-21swapper09:27:220
4704991230603,625cyclictest0-21swapper12:02:570
4704991229606,621cyclictest0-21swapper10:59:490
4704991227599,626cyclictest0-21swapper07:41:120
4704991226596,628cyclictest0-21swapper12:11:100
4704991224596,626cyclictest0-21swapper10:08:240
4704991223591,630cyclictest0-21swapper10:35:520
4704991222596,624cyclictest0-21swapper08:29:260
4704991221621,597cyclictest21290-21sh11:56:450
4704991221602,617cyclictest0-21swapper12:28:140
4704991218619,595cyclictest6209-21ls08:30:160
4704991218594,622cyclictest0-21swapper08:20:030
4704991217593,622cyclictest0-21swapper08:00:570
4704991215584,629cyclictest0-21swapper10:46:150
4704991213588,623cyclictest0-21swapper09:24:110
4704991210582,626cyclictest0-21swapper08:35:470
4704991207584,621cyclictest0-21swapper11:41:410
4704991207580,625cyclictest0-21swapper11:32:380
4704991205576,627cyclictest0-21swapper09:41:260
4704991204576,626cyclictest0-21swapper08:50:220
4704991196572,622cyclictest0-21swapper11:21:150
4704991196570,624cyclictest0-21swapper08:59:440
4704991194569,623cyclictest0-21swapper11:48:430
4704991192565,625cyclictest0-21swapper09:02:050
4704991184554,628cyclictest0-21swapper09:56:210
4704991182555,625cyclictest0-21swapper10:42:240
4704991182549,631cyclictest0-21swapper08:10:200
4704991180604,574cyclictest20909-21ssh11:14:430
4704991180551,627cyclictest0-21swapper10:01:520
4704991178600,575cyclictest15865-21ls10:25:190
4704991169597,569cyclictest5000-21ssh10:53:470
4704991158532,624cyclictest0-21swapper09:34:040
4704991154527,625cyclictest0-21swapper07:34:100
4704991147523,622cyclictest0-21swapper12:39:380
4704991144519,623cyclictest0-21swapper07:16:250
4704991144514,628cyclictest0-21swapper07:53:050
4704991143526,615cyclictest0-21swapper08:08:300
4704991143522,619cyclictest0-21swapper09:16:090
4704991138518,618cyclictest0-21swapper07:28:080
4704991135510,623cyclictest0-21swapper10:11:250
4704991122477,643cyclictest0-21swapper09:37:350
4704991120497,621cyclictest0-21swapper10:33:210
4704991110485,623cyclictest0-21swapper08:44:200
4704991106478,626cyclictest0-21swapper11:02:200
4704991068543,522cyclictest22856-21ssh09:10:170
470499954590,362cyclictest30186-21ssh12:08:590
470499853614,236cyclictest22089-21diskmemload11:54:550
470499742584,156cyclictest31127-21ssh11:27:270
470499718472,243cyclictest20999-21abrt-action-sav09:05:260
4704996388,628cyclictest0-21swapper07:20:060
373527254,14sleep00-21swapper07:05:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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