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2022-05-23 - 05:10

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6.osadl.org (updated Fri May 20, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76469951742644,2527cyclictest1724-21hald20:40:170
76469945832430,2150cyclictest1724-21hald23:33:470
7646991258625,631cyclictest0-21swapper00:06:460
7646991254613,639cyclictest0-21swapper22:42:120
7646991241613,626cyclictest0-21swapper23:46:200
7646991241613,626cyclictest0-21swapper21:26:400
7646991239612,625cyclictest0-21swapper21:58:290
7646991239611,626cyclictest0-21swapper00:39:460
7646991233612,619cyclictest0-21swapper19:50:520
7646991230606,622cyclictest0-21swapper23:52:320
7646991221595,624cyclictest0-21swapper22:24:470
7646991221587,632cyclictest0-21swapper23:03:280
7646991217592,623cyclictest0-21swapper22:58:260
7646991217592,623cyclictest0-21swapper22:16:340
7646991215591,622cyclictest0-21swapper23:23:340
7646991213591,620cyclictest0-21swapper00:04:250
7646991212589,621cyclictest0-21swapper23:11:500
7646991207580,625cyclictest0-21swapper20:16:400
7646991207577,628cyclictest0-21swapper19:57:140
7646991207576,629cyclictest0-21swapper20:35:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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