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2026-04-14 - 02:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Apr 14, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
177279910704153479,53438cyclictest21922-21ssh21:37:360
177279910688153464,53351cyclictest134850irq/9-eth022:25:200
177279910674253416,53262cyclictest9-21ksoftirqd/022:45:060
177279910670153427,53179cyclictest2755-21diskmemload23:19:050
177279910655253390,53097cyclictest0-21swapper22:13:160
177279910655153389,53096cyclictest0-21swapper00:03:280
177279910652453449,53075cyclictest0-21swapper20:26:060
177279910651153472,53039cyclictest0-21swapper21:03:260
177279910649753422,53075cyclictest0-21swapper23:42:320
177279910648553462,53023cyclictest0-21swapper00:39:290
177279910648353418,53065cyclictest0-21swapper22:32:320
177279910647353411,53062cyclictest0-21swapper21:25:330
177279910646353407,53056cyclictest0-21swapper21:57:420
177279910644953470,52979cyclictest0-21swapper20:44:010
177279910643953392,53047cyclictest0-21swapper19:36:010
177279910643853393,53045cyclictest0-21swapper22:35:530
177279910640253476,52862cyclictest17720-21cyclictest20:14:020
177279910638753424,52900cyclictest17720-21cyclictest19:22:170
177279910635553463,52892cyclictest0-21swapper23:25:470
177279910635453462,52892cyclictest0-21swapper20:47:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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