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2021-07-28 - 07:09

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6.osadl.org (updated Wed Jul 28, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
96749921351328,804cyclictest2582-21devkit-power-da19:28:140
9674991254614,638cyclictest0-21swapper00:09:250
9674991251622,627cyclictest0-21swapper20:57:290
9674991247620,625cyclictest0-21swapper22:17:420
9674991247620,625cyclictest0-21swapper20:08:550
9674991244614,628cyclictest0-21swapper20:10:160
9674991243618,623cyclictest0-21swapper22:51:520
9674991240612,626cyclictest0-21swapper20:18:280
9674991238614,622cyclictest0-21swapper21:56:060
9674991238614,622cyclictest0-21swapper19:51:200
9674991234606,626cyclictest0-21swapper20:27:000
9674991233607,624cyclictest0-21swapper21:32:090
9674991232604,626cyclictest0-21swapper22:47:110
9674991230600,628cyclictest0-21swapper19:38:570
9674991229603,624cyclictest0-21swapper21:15:040
9674991227605,620cyclictest0-21swapper23:20:000
9674991226600,624cyclictest0-21swapper23:07:170
9674991224601,621cyclictest0-21swapper21:03:110
9674991224597,625cyclictest0-21swapper21:23:570
9674991223600,621cyclictest0-21swapper00:20:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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