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2019-07-16 - 03:15

Intel(R) Celeron(R) M processor 1.60GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6.osadl.org (updated Mon Jul 15, 2019 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321529926402625,13cyclictest1811-21hald00:09:320
3215299746738,6cyclictest10853-21sensors22:52:040
3215299667659,6cyclictest1331-21sensors00:47:020
3215299660651,7cyclictest1963-21snmpd21:11:530
32152996508,6cyclictest3885-21ssh23:26:290
32152996477,638cyclictest0-21swapper00:28:470
32152996467,637cyclictest0-21swapper01:47:500
32152996447,635cyclictest0-21swapper22:04:050
32152996447,635cyclictest0-21swapper21:59:540
32152996437,634cyclictest0-21swapper23:46:350
32152996437,634cyclictest0-21swapper20:37:400
32152996437,634cyclictest0-21swapper00:42:110
32152996427,633cyclictest0-21swapper00:33:190
32152996427,632cyclictest4744-21ssh22:44:270
32152996407,631cyclictest0-21swapper20:33:590
32152996397,630cyclictest0-21swapper22:41:360
32152996397,630cyclictest0-21swapper00:12:330
32152996387,629cyclictest0-21swapper23:48:060
32152996387,4cyclictest0-21swapper21:05:380
32152996387,4cyclictest0-21swapper01:18:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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