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2021-10-23 - 20:32

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6.osadl.org (updated Sat Oct 23, 2021 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20826991251620,629cyclictest0-21swapper08:02:390
20826991246620,624cyclictest0-21swapper12:16:230
20826991246616,628cyclictest0-21swapper08:50:330
20826991245619,624cyclictest0-21swapper11:43:130
20826991244617,625cyclictest0-21swapper07:41:540
20826991244605,637cyclictest0-21swapper11:32:400
20826991243617,624cyclictest0-21swapper09:07:480
20826991238607,629cyclictest0-21swapper12:04:190
20826991238604,632cyclictest0-21swapper07:31:410
20826991233613,618cyclictest0-21swapper08:11:520
20826991233606,625cyclictest0-21swapper09:18:510
20826991233605,626cyclictest0-21swapper11:11:240
20826991233596,635cyclictest0-21swapper10:12:170
20826991231604,625cyclictest0-21swapper07:25:290
20826991229601,626cyclictest0-21swapper08:18:140
20826991228605,621cyclictest0-21swapper11:29:090
20826991225598,625cyclictest0-21swapper08:30:170
20826991224600,622cyclictest0-21swapper12:29:560
20826991224597,625cyclictest0-21swapper08:38:000
20826991221600,619cyclictest0-21swapper07:46:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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