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2021-04-15 - 01:56

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6.osadl.org (updated Thu Apr 15, 2021 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70759925332524,7cyclictest1724-21hald20:52:280
7075991247620,625cyclictest0-21swapper20:00:330
7075991247619,626cyclictest0-21swapper22:47:010
7075991244617,625cyclictest0-21swapper19:25:120
7075991238611,625cyclictest0-21swapper19:16:200
7075991237615,620cyclictest0-21swapper19:54:410
7075991235615,619cyclictest0-21swapper00:29:000
7075991235614,619cyclictest0-21swapper19:39:260
7075991234614,618cyclictest0-21swapper19:12:090
7075991234613,619cyclictest0-21swapper00:09:240
7075991234609,623cyclictest0-21swapper20:36:030
7075991233613,618cyclictest0-21swapper20:23:090
7075991231603,626cyclictest0-21swapper20:42:050
7075991230606,622cyclictest0-21swapper20:28:210
7075991230603,625cyclictest0-21swapper23:36:250
7075991229607,620cyclictest0-21swapper00:17:270
7075991228601,625cyclictest0-21swapper19:40:570
7075991225600,623cyclictest0-21swapper23:50:290
7075991224597,625cyclictest0-21swapper23:34:340
7075991222600,620cyclictest0-21swapper22:15:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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