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2022-12-02 - 17:28

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 376 highest latencies:
System rack6slot6.osadl.org (updated Fri Dec 02, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82649910511153038,52071cyclictest0-21swapper11:35:420
82649910496352907,52055cyclictest0-21swapper07:40:450
82649951302585,2542cyclictest1724-21hald11:08:250
8264991262621,639cyclictest0-21swapper11:25:400
8264991260615,16cyclictest0-21swapper10:32:240
8264991255623,630cyclictest0-21swapper10:07:070
8264991252622,628cyclictest0-21swapper10:01:050
8264991251619,630cyclictest0-21swapper12:34:390
8264991251618,631cyclictest0-21swapper10:12:280
8264991249616,631cyclictest0-21swapper09:33:570
8264991243614,627cyclictest0-21swapper09:21:040
8264991241612,626cyclictest0-21swapper07:17:380
8264991241607,632cyclictest0-21swapper09:00:580
8264991239612,625cyclictest0-21swapper12:27:470
8264991238610,626cyclictest0-21swapper07:56:090
8264991237609,626cyclictest0-21swapper11:33:420
8264991236611,623cyclictest0-21swapper12:09:020
8264991235603,630cyclictest0-21swapper07:49:270
8264991231601,628cyclictest0-21swapper09:55:030
8264991230598,630cyclictest0-21swapper12:24:570
8264991228599,627cyclictest0-21swapper09:09:300
8264991228599,627cyclictest0-21swapper08:02:210
8264991227598,627cyclictest0-21swapper08:57:070
8264991226596,628cyclictest0-21swapper11:48:460
8264991225596,627cyclictest0-21swapper10:27:230
8264991224596,626cyclictest0-21swapper09:53:430
8264991223595,626cyclictest0-21swapper10:58:220
8264991222593,627cyclictest0-21swapper08:23:570
8264991221596,623cyclictest0-21swapper09:13:310
8264991219592,625cyclictest0-21swapper09:25:450
8264991219591,626cyclictest0-21swapper07:13:570
8264991218590,626cyclictest0-21swapper07:33:430
8264991216586,628cyclictest0-21swapper08:33:200
8264991213591,620cyclictest0-21swapper11:43:550
8264991213575,636cyclictest0-21swapper07:23:500
8264991210585,623cyclictest0-21swapper10:19:100
8264991208580,626cyclictest0-21swapper11:50:070
8264991208580,626cyclictest0-21swapper08:07:120
8264991205578,625cyclictest0-21swapper09:37:380
8264991202609,589cyclictest26103-21ls12:35:200
8264991201581,618cyclictest0-21swapper12:03:200
8264991199572,625cyclictest0-21swapper10:45:580
8264991198576,620cyclictest0-21swapper10:50:090
8264991193565,626cyclictest0-21swapper07:26:310
8264991183561,620cyclictest0-21swapper11:03:430
8264991180551,627cyclictest0-21swapper08:15:550
8264991178547,629cyclictest0-21swapper07:39:040
8264991171552,617cyclictest0-21swapper08:37:410
8264991170598,569cyclictest8514-21users08:25:280
8264991170535,633cyclictest0-21swapper09:47:010
8264991166540,624cyclictest0-21swapper08:14:340
8264991162596,564cyclictest6547-21ssh12:10:220
8264991151527,622cyclictest0-21swapper08:54:160
8264991150524,624cyclictest0-21swapper08:47:040
8264991148516,630cyclictest0-21swapper11:57:290
8264991147522,623cyclictest0-21swapper10:36:050
8264991139508,629cyclictest0-21swapper08:43:430
8264991125488,635cyclictest0-21swapper09:41:090
8264991122492,628cyclictest0-21swapper11:15:060
8264991096466,628cyclictest0-21swapper09:15:020
8264991093468,623cyclictest0-21swapper10:40:060
8264991093466,625cyclictest0-21swapper12:18:150
8264991086462,622cyclictest0-21swapper11:14:160
826499917473,442cyclictest10-21rcuc/011:20:280
826499893460,430cyclictest25559-21iostat_ios07:50:170
826499888561,325cyclictest131550irq/9-eth010:23:520
752827655,17sleep00-21swapper07:06:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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