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2024-04-24 - 00:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Tue Apr 23, 2024 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1987199210845105346,105497cyclictest0-21swapper10:07:130
1987199209797105302,104494cyclictest0-21swapper10:13:550
198719910703153410,53530cyclictest0-21swapper09:58:200
198719910675853458,53300cyclictest0-21swapper08:33:160
198719910670653446,53260cyclictest0-21swapper07:53:140
198719910664753439,53116cyclictest11-21rcu_preempt08:15:310
198719910661353418,53100cyclictest4823-21diskmemload12:23:220
198719910658153466,53115cyclictest0-21swapper08:53:120
198719910655053386,53099cyclictest0-21swapper08:08:390
198719910653953445,53094cyclictest0-21swapper09:44:060
198719910649053473,53017cyclictest0-21swapper08:37:370
198719910649053450,53040cyclictest0-21swapper12:13:390
198719910646953478,52991cyclictest0-21swapper09:36:240
198719910644653447,52999cyclictest0-21swapper09:14:280
198719910642853403,53025cyclictest0-21swapper08:39:580
198719910638753434,52888cyclictest21542-21kworker/0:311:01:290
198719910628053423,52765cyclictest0-21swapper11:05:000
198719910627953446,52833cyclictest0-21swapper07:19:550
198719910627853458,52820cyclictest0-21swapper08:26:240
198719910625053385,52800cyclictest0-21swapper10:20:070
198719910624953382,52804cyclictest0-21swapper08:01:470
198719910621453442,52772cyclictest0-21swapper07:25:560
198719910621353470,52743cyclictest0-21swapper07:49:030
198719910619753461,52736cyclictest0-21swapper11:49:220
198719910618453412,52772cyclictest0-21swapper07:57:260
198719910617353409,52764cyclictest0-21swapper07:31:480
198719910616253402,52760cyclictest0-21swapper08:47:500
198719910615953445,52714cyclictest0-21swapper09:00:040
198719910614053435,52705cyclictest0-21swapper07:09:220
198719910610153027,53072cyclictest0-21swapper12:29:240
198719910608552986,53094cyclictest0-21swapper10:25:180
198719910606653004,53060cyclictest0-21swapper12:00:560
198719910603252986,53044cyclictest0-21swapper12:04:470
198719910599752913,53082cyclictest0-21swapper11:46:520
198719910595452913,53039cyclictest0-21swapper09:19:290
198719910588053029,52844cyclictest2109-21runrttasks10:35:110
198719910540353002,52395cyclictest25694-21kworker/u2:110:34:110
198719910530653054,52249cyclictest12559-21ssh11:29:470
198719910516153061,52098cyclictest0-21swapper08:11:400
198719910515753048,52107cyclictest0-21swapper11:57:550
198719910515253038,52112cyclictest0-21swapper10:39:320
198719910514053030,52108cyclictest0-21swapper11:43:410
198719910509752997,52098cyclictest0-21swapper11:35:080
198719910508852988,52098cyclictest0-21swapper12:29:140
198719910503352976,52055cyclictest0-21swapper12:37:160
198719910502352920,52101cyclictest0-21swapper11:26:260
198719910500352916,52085cyclictest0-21swapper07:14:330
19871995351525,53490cyclictest0-21swapper09:24:210
19871995334128,0cyclictest15754-21ssh12:19:010
1987199531268,53116cyclictest0-21swapper09:52:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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