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2021-01-19 - 06:41

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6.osadl.org (updated Tue Jan 19, 2021 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244479910728553482,53707cyclictest22238-21diskmemload00:34:410
244479910699253384,53543cyclictest134950irq/9-eth000:02:520
244479910691753413,53440cyclictest32701-21kworker/0:200:23:480
244479910677453400,53277cyclictest1940-21ssh00:05:430
244479910661653428,53097cyclictest0-21swapper23:10:370
244479910656253473,53089cyclictest0-21swapper20:39:540
244479910655153394,53093cyclictest9-21ksoftirqd/022:36:070
244479910653653400,53039cyclictest1909-21snmpd20:09:150
244479910649953474,53025cyclictest0-21swapper20:18:480
244479910647853459,53019cyclictest0-21swapper19:44:080
244479910646153411,53050cyclictest0-21swapper20:28:400
244479910645253451,53001cyclictest0-21swapper23:29:530
244479910642853392,53036cyclictest0-21swapper22:51:110
244479910642453437,52987cyclictest0-21swapper23:59:110
244479910639953416,52983cyclictest0-21swapper23:50:390
244479910638053426,52891cyclictest24443-21cyclictest00:12:150
244479910631053365,52852cyclictest0-21swapper20:02:430
244479910624953440,52809cyclictest0-21swapper20:47:360
244479910620453463,52741cyclictest0-21swapper21:06:410
244479910620353464,52739cyclictest0-21swapper20:31:110
244479910620053472,52728cyclictest0-21swapper23:18:190
244479910614553434,52711cyclictest0-21swapper20:22:590
244479910613953426,52713cyclictest0-21swapper19:48:190
244479910613453442,52692cyclictest0-21swapper21:01:000
244479910612953426,52703cyclictest0-21swapper20:12:260
244479910511553031,52084cyclictest0-21swapper23:34:040
2444799537046,0cyclictest0-21swapper23:09:070
24447995364053369,207cyclictest0-21swapper20:42:340
24447995363825,53547cyclictest3950irq/9-acpi22:01:170
24447995359326,498cyclictest0-21swapper23:01:140
24447995348153381,36cyclictest26521-21kworker/0:319:33:240
24447995346225,53343cyclictest0-21swapper20:50:470
24447995329624,0cyclictest0-21swapper20:57:490
24447995318624,53162cyclictest0-21swapper19:58:220
24447995306424,53040cyclictest0-21swapper22:17:020
244479922801101,1179cyclictest28022-21ssh22:27:550
244479922601068,1063cyclictest30334-21ssh21:46:230
244479922501009,1114cyclictest16770-21ssh23:42:060
244479922441023,1096cyclictest6338-21ssh21:12:330
24447992164973,1096cyclictest0-21swapper21:40:210
244479921291027,1010cyclictest3950irq/9-acpi21:30:380
244479921141088,934cyclictest9-21ksoftirqd/022:43:090
244479921071032,1009cyclictest3950irq/9-acpi23:48:380
244479921041045,1024cyclictest0-21swapper19:25:520
244479920751016,967cyclictest3950irq/9-acpi22:23:330
244479920411001,1005cyclictest0-21swapper23:38:150
244479920251017,914cyclictest24443-21cyclictest00:39:330
244479919711016,863cyclictest31103-21kworker/0:022:34:570
244479919681017,860cyclictest0-21swapper21:57:160
24447991958918,1005cyclictest0-21swapper21:54:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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