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2022-06-27 - 17:17

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6.osadl.org (updated Mon Jun 27, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266369946112522,2086cyclictest1724-21hald07:51:000
26636991247616,629cyclictest0-21swapper07:35:450
26636991245619,624cyclictest0-21swapper11:15:080
26636991245617,626cyclictest0-21swapper09:10:420
26636991240612,626cyclictest0-21swapper12:13:250
26636991238611,625cyclictest0-21swapper10:06:290
26636991237611,624cyclictest0-21swapper12:25:390
26636991236614,620cyclictest0-21swapper07:46:080
26636991236607,627cyclictest0-21swapper11:09:070
26636991235611,622cyclictest0-21swapper11:22:100
26636991231603,626cyclictest0-21swapper08:47:560
26636991228598,628cyclictest0-21swapper11:26:120
26636991224597,625cyclictest0-21swapper12:24:280
26636991223607,614cyclictest0-21swapper10:53:320
26636991222602,618cyclictest0-21swapper10:42:290
26636991222600,620cyclictest0-21swapper08:01:120
26636991220595,623cyclictest0-21swapper08:51:070
26636991218597,619cyclictest0-21swapper07:43:170
26636991215600,613cyclictest0-21swapper07:31:540
26636991215589,624cyclictest0-21swapper11:57:100
26636991215587,626cyclictest0-21swapper08:44:150
26636991214619,592cyclictest27842-21iostat_ios09:30:180
26636991213591,620cyclictest0-21swapper09:08:520
26636991212586,624cyclictest0-21swapper08:11:350
26636991212582,628cyclictest0-21swapper10:34:370
26636991211619,589cyclictest26660-21grep08:26:000
26636991211587,622cyclictest0-21swapper10:45:500
26636991211586,623cyclictest0-21swapper11:30:130
26636991211574,635cyclictest0-21swapper10:14:310
26636991208619,586cyclictest11727-21diskmemload09:24:470
26636991208580,626cyclictest0-21swapper12:17:460
26636991205619,583cyclictest21178-21ssh10:04:080
26636991200568,630cyclictest0-21swapper08:07:440
26636991195615,578cyclictest11505-21ssh09:50:340
26636991195567,626cyclictest0-21swapper10:28:450
26636991193566,625cyclictest0-21swapper11:45:370
26636991191611,577cyclictest22315-21ls08:15:270
26636991191567,622cyclictest0-21swapper11:54:500
26636991191564,625cyclictest0-21swapper11:35:540
26636991188562,624cyclictest0-21swapper08:58:490
26636991182557,623cyclictest0-21swapper07:55:010
26636991177558,617cyclictest0-21swapper10:59:240
26636991175545,628cyclictest0-21swapper11:13:080
26636991167541,624cyclictest0-21swapper07:14:090
26636991165539,624cyclictest0-21swapper10:37:270
26636991165539,624cyclictest0-21swapper10:20:530
26636991164535,627cyclictest0-21swapper09:46:130
26636991162536,624cyclictest0-21swapper07:20:410
26636991155531,622cyclictest0-21swapper11:44:570
26636991154523,629cyclictest0-21swapper08:31:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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