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2023-01-30 - 06:21

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6.osadl.org (updated Mon Jan 30, 2023 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118059910559352888,52702cyclictest6911-21find20:10:320
118059910498452924,52059cyclictest0-21swapper19:31:110
11805995306753042,24cyclictest0-21swapper21:21:120
11805991251621,628cyclictest0-21swapper20:18:240
11805991249617,630cyclictest0-21swapper00:24:150
11805991248618,628cyclictest0-21swapper20:27:470
11805991245615,628cyclictest0-21swapper21:00:160
11805991244618,624cyclictest0-21swapper19:23:180
11805991244610,632cyclictest0-21swapper22:09:460
11805991242609,631cyclictest0-21swapper22:32:030
11805991240615,623cyclictest0-21swapper22:28:320
11805991240610,628cyclictest0-21swapper19:56:080
11805991234605,627cyclictest0-21swapper22:43:360
11805991233609,622cyclictest0-21swapper20:53:040
11805991233609,622cyclictest0-21swapper20:43:210
11805991232614,616cyclictest0-21swapper00:04:590
11805991231603,625cyclictest0-21swapper21:54:420
11805991230576,15cyclictest0-21swapper22:22:000
11805991228605,621cyclictest0-21swapper21:30:450
11805991225600,623cyclictest0-21swapper23:14:050
11805991223596,625cyclictest0-21swapper20:09:420
11805991221584,635cyclictest0-21swapper00:16:530
11805991221580,639cyclictest0-21swapper19:12:050
11805991220592,626cyclictest0-21swapper00:36:080
11805991216593,621cyclictest0-21swapper20:39:300
11805991209585,622cyclictest0-21swapper20:59:360
11805991208583,623cyclictest0-21swapper00:30:470
11805991208575,631cyclictest0-21swapper22:15:380
11805991207581,624cyclictest0-21swapper19:35:520
11805991206579,625cyclictest0-21swapper00:28:460
11805991203581,620cyclictest0-21swapper19:46:450
11805991197573,622cyclictest0-21swapper00:14:120
11805991194566,626cyclictest0-21swapper22:49:380
11805991194563,629cyclictest0-21swapper22:14:280
11805991191561,628cyclictest0-21swapper22:58:200
11805991188563,623cyclictest0-21swapper00:08:100
11805991180548,630cyclictest0-21swapper23:21:270
11805991179555,622cyclictest0-21swapper23:26:380
11805991179555,622cyclictest0-21swapper21:39:480
11805991174544,628cyclictest0-21swapper20:34:190
11805991173552,619cyclictest0-21swapper21:40:580
11805991173550,621cyclictest0-21swapper23:57:270
11805991171528,641cyclictest0-21swapper19:19:270
11805991165536,627cyclictest0-21swapper20:04:300
11805991162531,629cyclictest0-21swapper23:51:250
11805991161516,642cyclictest0-21swapper22:37:140
11805991159530,627cyclictest0-21swapper21:59:530
11805991152529,621cyclictest0-21swapper21:15:510
11805991148520,626cyclictest0-21swapper23:48:450
11805991142517,623cyclictest0-21swapper20:46:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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