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2022-01-26 - 12:48

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6.osadl.org (updated Wed Jan 26, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106799944192628,1788cyclictest2582-21devkit-power-da21:10:100
10679991248620,626cyclictest0-21swapper23:26:290
10679991248620,626cyclictest0-21swapper20:21:050
10679991247620,625cyclictest0-21swapper22:44:070
10679991242614,626cyclictest0-21swapper19:28:300
10679991241617,622cyclictest0-21swapper22:34:340
10679991241616,624cyclictest0-21swapper21:41:180
10679991240612,626cyclictest0-21swapper21:31:360
10679991237607,628cyclictest0-21swapper21:07:090
10679991236610,624cyclictest0-21swapper19:15:060
10679991235609,624cyclictest0-21swapper23:22:280
10679991234612,620cyclictest0-21swapper20:42:110
10679991234610,622cyclictest0-21swapper23:16:460
10679991232604,626cyclictest0-21swapper22:59:410
10679991232604,626cyclictest0-21swapper20:45:120
10679991231612,617cyclictest0-21swapper00:12:420
10679991231611,618cyclictest0-21swapper19:10:550
10679991229610,617cyclictest0-21swapper19:24:390
10679991229607,620cyclictest0-21swapper19:46:560
10679991226597,627cyclictest0-21swapper19:38:330
10679991225597,626cyclictest0-21swapper20:32:090
10679991224600,622cyclictest0-21swapper22:02:550
10679991221594,625cyclictest0-21swapper20:53:150
10679991221572,647cyclictest0-21swapper22:22:300
10679991220601,617cyclictest0-21swapper22:46:570
10679991220595,623cyclictest0-21swapper21:03:180
10679991219597,620cyclictest0-21swapper00:17:130
10679991215591,622cyclictest0-21swapper22:09:370
10679991215588,625cyclictest0-21swapper23:04:530
10679991213591,620cyclictest0-21swapper00:26:560
10679991212591,620cyclictest0-21swapper20:10:520
10679991212587,623cyclictest0-21swapper23:40:430
10679991208589,617cyclictest0-21swapper20:05:510
10679991205578,625cyclictest0-21swapper22:36:140
10679991203575,626cyclictest0-21swapper21:39:580
10679991202576,624cyclictest0-21swapper23:08:240
10679991202571,629cyclictest0-21swapper00:06:100
10679991196571,623cyclictest0-21swapper20:03:100
10679991196567,627cyclictest0-21swapper20:17:440
10679991194572,620cyclictest0-21swapper00:36:390
10679991194566,626cyclictest0-21swapper22:13:380
10679991186565,619cyclictest0-21swapper21:24:140
10679991177551,624cyclictest0-21swapper19:59:090
10679991174543,629cyclictest0-21swapper23:55:370
10679991173548,623cyclictest0-21swapper22:26:010
10679991171550,619cyclictest0-21swapper22:50:490
10679991171547,622cyclictest0-21swapper21:55:530
10679991164538,624cyclictest0-21swapper00:31:580
10679991163538,623cyclictest0-21swapper21:47:100
10679991158532,624cyclictest0-21swapper20:38:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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