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2024-06-17 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Mon Jun 17, 2024 00:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204919910729453468,53725cyclictest25355-21rm21:42:190
204919910721053472,53615cyclictest10433-21ssh00:30:580
204919910701753473,53447cyclictest19166-21ssh23:12:150
204919910699253461,53410cyclictest5552-21diskmemload22:47:580
204919910684953455,53330cyclictest191042sleep020:23:460
204919910664653470,53176cyclictest0-21swapper00:39:100
204919910660853416,53126cyclictest0-21swapper23:02:120
204919910659653429,53167cyclictest0-21swapper19:10:050
204919910659053370,53131cyclictest9-21ksoftirqd/021:32:560
204919910657453411,53071cyclictest0-21swapper00:28:070
204919910655553426,53129cyclictest0-21swapper00:07:110
204919910654153399,53142cyclictest0-21swapper21:57:440
204919910652253397,53125cyclictest0-21swapper19:30:110
204919910650953467,53042cyclictest0-21swapper23:08:440
204919910650653463,53043cyclictest0-21swapper21:07:590
204919910650453470,53034cyclictest0-21swapper20:27:380
204919910648553460,53025cyclictest0-21swapper20:03:110
204919910647653444,53032cyclictest0-21swapper19:35:230
204919910645953456,53003cyclictest0-21swapper20:39:010
204919910644653447,52999cyclictest0-21swapper21:25:440
204919910644253444,52998cyclictest0-21swapper00:03:300
204919910642053458,52962cyclictest0-21swapper21:04:080
204919910641653407,53009cyclictest0-21swapper20:57:060
204919910636853476,52892cyclictest0-21swapper20:41:520
204919910632553306,53007cyclictest3950irq/9-acpi22:30:530
204919910630253379,52859cyclictest9-21ksoftirqd/019:23:590
204919910629053389,52810cyclictest0-21swapper20:12:230
204919910626653448,52704cyclictest0-21swapper20:47:030
204919910625653388,52803cyclictest0-21swapper19:15:270
204919910624053445,52704cyclictest0-21swapper00:13:330
204919910620853468,52740cyclictest0-21swapper22:57:310
204919910618553415,52770cyclictest0-21swapper20:51:240
204919910616553404,52761cyclictest0-21swapper23:27:390
204919910615553061,53092cyclictest0-21swapper22:42:360
204919910602753363,52664cyclictest0-21swapper19:25:000
204919910515653047,52107cyclictest0-21swapper23:55:070
204919910508752992,52093cyclictest0-21swapper21:22:430
20491995385953394,465cyclictest0-21swapper19:56:390
20491995366653396,207cyclictest2526050irq/9-eth000:21:350
20491995344924,53425cyclictest0-21swapper20:17:050
20491995317130,53049cyclictest9-21ksoftirqd/019:49:170
204919924271074,1253cyclictest21654-21ssh23:15:060
204919923691022,1220cyclictest1639-21ssh23:34:010
204919922891073,1122cyclictest3950irq/9-acpi22:07:560
204919921931098,1001cyclictest2526050irq/9-eth021:34:270
204919921021034,975cyclictest12059-21rm22:15:590
204919920471082,871cyclictest9-21ksoftirqd/023:38:430
204919920331019,976cyclictest5985-21ssh22:54:100
204919919791020,925cyclictest0-21swapper21:45:200
204919919521004,913cyclictest0-21swapper23:46:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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