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2022-07-06 - 00:51

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 792 highest latencies:
System rack6slot6.osadl.org (updated Tue Jul 05, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157369925421702,837cyclictest1724-21hald12:39:430
15736991259626,631cyclictest0-21swapper10:10:400
15736991245618,625cyclictest0-21swapper08:35:520
15736991244615,627cyclictest0-21swapper09:06:010
15736991244613,629cyclictest0-21swapper09:24:060
15736991243616,625cyclictest0-21swapper11:52:090
15736991241613,626cyclictest0-21swapper07:46:080
15736991241608,631cyclictest0-21swapper09:58:160
15736991240615,623cyclictest0-21swapper07:57:510
15736991240613,625cyclictest0-21swapper12:00:510
15736991239616,621cyclictest0-21swapper08:15:460
15736991236610,624cyclictest0-21swapper08:55:580
15736991235614,619cyclictest0-21swapper12:13:550
15736991235613,620cyclictest0-21swapper08:49:260
15736991235605,628cyclictest0-21swapper08:07:540
15736991234612,620cyclictest0-21swapper10:02:270
15736991234605,627cyclictest0-21swapper08:42:140
15736991233608,623cyclictest0-21swapper12:21:370
15736991229602,625cyclictest0-21swapper08:53:370
15736991227597,628cyclictest0-21swapper11:14:180
15736991226600,624cyclictest0-21swapper11:37:040
15736991222604,617cyclictest0-21swapper12:28:290
15736991217592,623cyclictest0-21swapper11:06:160
15736991216593,621cyclictest0-21swapper09:01:500
15736991215591,622cyclictest0-21swapper07:54:500
15736991213587,624cyclictest0-21swapper07:24:520
15736991213580,631cyclictest0-21swapper11:03:550
15736991209584,623cyclictest0-21swapper09:30:480
15736991207576,629cyclictest0-21swapper07:33:540
15736991204575,627cyclictest0-21swapper09:38:100
15736991197571,624cyclictest0-21swapper09:47:230
15736991197571,624cyclictest0-21swapper08:01:520
15736991195566,627cyclictest0-21swapper12:15:150
15736991194570,622cyclictest0-21swapper09:42:310
15736991193568,623cyclictest0-21swapper09:28:170
15736991192557,633cyclictest0-21swapper11:49:280
15736991189560,627cyclictest0-21swapper09:54:350
15736991188554,632cyclictest0-21swapper10:18:320
15736991186565,619cyclictest0-21swapper09:14:130
15736991186561,623cyclictest0-21swapper11:31:030
15736991181555,624cyclictest0-21swapper07:44:480
15736991180558,620cyclictest0-21swapper10:38:280
15736991180558,620cyclictest0-21swapper10:32:460
15736991180554,624cyclictest0-21swapper12:30:300
15736991180552,626cyclictest0-21swapper07:38:260
15736991179555,622cyclictest0-21swapper08:13:460
15736991178558,618cyclictest0-21swapper10:46:200
15736991177551,624cyclictest0-21swapper11:58:110
15736991174547,625cyclictest0-21swapper11:15:180
15736991172617,553cyclictest13977-21ssh10:08:590
15736991170555,613cyclictest0-21swapper07:28:130
15736991170546,622cyclictest0-21swapper08:28:000
15736991166545,619cyclictest0-21swapper07:14:390
15736991165544,619cyclictest0-21swapper08:22:480
15736991153606,544cyclictest8315-21ls11:25:210
15736991150525,623cyclictest0-21swapper08:34:220
15736991149524,623cyclictest0-21swapper07:15:090
15736991145505,638cyclictest0-21swapper10:41:380
15736991142520,620cyclictest0-21swapper12:07:230
15736991139516,621cyclictest0-21swapper09:18:550
15736991138514,622cyclictest0-21swapper10:53:320
15736991133510,621cyclictest0-21swapper10:58:030
15736991122504,616cyclictest0-21swapper11:44:570
15736991109582,524cyclictest28659-21rm10:27:440
15736991096471,623cyclictest0-21swapper11:23:100
1573699736599,135cyclictest23158-21strings10:20:220
1558727255,13sleep00-21swapper07:09:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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