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2022-12-09 - 17:57

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of all highest latencies:
System rack6slot6.osadl.org (updated Thu Dec 08, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292469950852777,2305cyclictest1724-21hald11:25:190
29246991259621,636cyclictest0-21swapper09:10:100
29246991251623,627cyclictest0-21swapper10:12:580
29246991250621,627cyclictest0-21swapper09:06:080
29246991247619,626cyclictest0-21swapper09:04:080
29246991245618,625cyclictest0-21swapper10:07:460
29246991237610,625cyclictest0-21swapper08:17:240
29246991236605,629cyclictest0-21swapper08:42:120
29246991235610,623cyclictest0-21swapper07:38:230
29246991232605,625cyclictest0-21swapper08:39:410
29246991231604,625cyclictest0-21swapper07:51:370
29246991230599,629cyclictest0-21swapper08:11:030
29246991229607,620cyclictest0-21swapper09:59:340
29246991229606,621cyclictest0-21swapper12:19:540
29246991229604,622cyclictest0-21swapper08:46:030
29246991228598,628cyclictest0-21swapper10:30:130
29246991227603,622cyclictest0-21swapper07:42:440
29246991225598,625cyclictest0-21swapper10:46:470
29246991221592,627cyclictest0-21swapper11:00:410
29246991221591,628cyclictest0-21swapper07:28:300
29246991212586,624cyclictest0-21swapper08:32:190
29246991212584,626cyclictest0-21swapper12:09:410
29246991202581,619cyclictest0-21swapper09:47:400
29246991201557,642cyclictest0-21swapper09:35:570
29246991200573,625cyclictest0-21swapper12:34:590
29246991199568,629cyclictest0-21swapper11:30:500
29246991196566,628cyclictest0-21swapper11:23:280
29246991191561,628cyclictest0-21swapper12:24:460
29246991190564,624cyclictest0-21swapper10:56:500
29246991184560,622cyclictest0-21swapper10:42:160
29246991182545,635cyclictest0-21swapper09:43:190
29246991181556,623cyclictest0-21swapper09:53:120
29246991180559,619cyclictest0-21swapper09:26:140
29246991176550,624cyclictest0-21swapper09:34:060
29246991175549,624cyclictest0-21swapper11:15:260
29246991175541,632cyclictest0-21swapper07:46:050
29246991173545,626cyclictest0-21swapper08:53:350
29246991171543,626cyclictest0-21swapper07:33:520
29246991168538,628cyclictest0-21swapper11:40:530
29246991166541,623cyclictest0-21swapper09:24:140
29246991165540,623cyclictest0-21swapper11:14:050
29246991160614,543cyclictest16231-21ssh10:28:220
29246991160530,628cyclictest0-21swapper12:14:330
29246991154527,625cyclictest0-21swapper08:07:110
29246991151522,627cyclictest0-21swapper10:24:110
29246991150517,631cyclictest0-21swapper10:52:490
29246991141512,627cyclictest0-21swapper12:37:390
29246991138504,632cyclictest0-21swapper08:57:560
29246991136510,624cyclictest0-21swapper10:01:440
29246991132508,622cyclictest0-21swapper08:20:350
29246991129503,624cyclictest0-21swapper07:58:590
29246991125502,621cyclictest0-21swapper09:19:320
29246991119490,627cyclictest0-21swapper11:35:210
29246991119489,628cyclictest0-21swapper07:17:370
29246991111478,631cyclictest0-21swapper10:16:590
29246991107484,621cyclictest0-21swapper07:12:560
29246991095466,627cyclictest0-21swapper08:01:400
29246991090468,620cyclictest0-21swapper10:37:350
29246991016543,470cyclictest16972-21ls12:25:260
2924699951511,437cyclictest25665-21ssh11:56:580
2924699935503,429cyclictest17348-21ssh11:46:550
2924699933500,430cyclictest27966-21ssh12:00:190
2924699919494,422cyclictest19432-21munin-node11:50:160
2924699857464,390cyclictest16637-21ssh11:07:230
29246996498,639cyclictest0-21swapper07:20:580
29246996418,631cyclictest0-21swapper08:26:470
2864327253,15sleep00-21swapper07:07:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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