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2022-07-03 - 08:33

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of all highest latencies:
System rack6slot6.osadl.org (updated Sun Jul 03, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21438991250622,627cyclictest0-21swapper00:34:240
21438991250620,628cyclictest0-21swapper20:52:100
21438991246619,625cyclictest0-21swapper22:34:290
21438991245619,624cyclictest0-21swapper00:23:410
21438991243618,623cyclictest0-21swapper21:19:580
21438991243615,626cyclictest0-21swapper23:52:520
21438991240613,625cyclictest0-21swapper22:07:310
21438991240612,626cyclictest0-21swapper20:23:510
21438991239611,626cyclictest0-21swapper21:34:020
21438991238611,625cyclictest0-21swapper20:58:210
21438991236610,624cyclictest0-21swapper21:25:390
21438991236606,628cyclictest0-21swapper22:47:530
21438991233610,621cyclictest0-21swapper21:39:430
21438991232607,623cyclictest0-21swapper22:59:560
21438991224600,622cyclictest0-21swapper19:20:030
21438991223600,621cyclictest0-21swapper20:06:360
21438991223599,622cyclictest0-21swapper21:12:350
21438991219593,624cyclictest0-21swapper22:20:550
21438991219590,627cyclictest0-21swapper22:50:340
21438991214590,622cyclictest0-21swapper22:02:400
21438991213582,629cyclictest0-21swapper20:34:550
21438991211590,619cyclictest0-21swapper21:55:180
21438991209582,625cyclictest0-21swapper19:32:370
21438991209576,631cyclictest0-21swapper19:27:250
21438991208590,616cyclictest0-21swapper20:10:280
21438991206580,624cyclictest0-21swapper23:46:200
21438991206576,628cyclictest0-21swapper23:35:470
21438991204579,623cyclictest0-21swapper19:46:410
21438991203569,632cyclictest0-21swapper21:24:590
21438991202573,627cyclictest0-21swapper20:00:050
21438991200577,621cyclictest0-21swapper21:49:260
21438991193573,618cyclictest0-21swapper20:19:200
21438991193568,623cyclictest0-21swapper19:15:420
21438991191569,620cyclictest0-21swapper22:19:150
21438991187563,622cyclictest0-21swapper23:18:020
21438991185560,623cyclictest0-21swapper23:10:500
21438991183561,620cyclictest0-21swapper21:05:430
21438991175549,624cyclictest0-21swapper22:40:110
21438991175546,627cyclictest0-21swapper00:25:310
21438991172546,624cyclictest0-21swapper00:13:180
21438991168534,632cyclictest0-21swapper23:27:140
21438991166541,623cyclictest0-21swapper22:12:430
21438991165535,628cyclictest0-21swapper19:39:290
21438991160529,629cyclictest0-21swapper22:26:370
21438991158537,619cyclictest0-21swapper21:42:240
21438991154531,621cyclictest0-21swapper21:52:470
21438991153616,534cyclictest4818-21strings23:55:220
21438991151530,619cyclictest0-21swapper23:01:570
21438991148616,530cyclictest12842-21ssh23:24:230
21438991143521,620cyclictest0-21swapper20:44:470
21438991140610,527cyclictest4336-21rm00:36:540
21438991140516,622cyclictest0-21swapper19:13:410
21438991139610,526cyclictest20426-21ssh00:15:280
21438991135500,633cyclictest0-21swapper00:02:340
21438991134514,618cyclictest0-21swapper19:52:120
21438991130504,624cyclictest0-21swapper21:04:230
21438991122500,620cyclictest0-21swapper23:09:390
21438991120490,628cyclictest0-21swapper20:37:350
21438991119485,632cyclictest0-21swapper19:43:100
21438991117492,623cyclictest0-21swapper00:09:060
21438991114483,629cyclictest0-21swapper23:40:480
21438991107481,624cyclictest0-21swapper20:48:490
21438991100469,629cyclictest0-21swapper19:55:130
21438991085458,625cyclictest0-21swapper23:34:560
21438991068448,618cyclictest0-21swapper20:25:520
2143899736510,223cyclictest8943-21ssh22:36:200
1994329178,7sleep02582-21devkit-power-da19:05:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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