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2021-10-17 - 04:31

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the alll highest latencies:
System rack6slot6.osadl.org (updated Sun Oct 17, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17745991246619,625cyclictest0-21swapper21:32:190
17745991245619,624cyclictest0-21swapper21:56:360
17745991242617,623cyclictest0-21swapper19:11:090
17745991241617,622cyclictest0-21swapper19:48:390
17745991241616,623cyclictest0-21swapper00:07:240
17745991241612,627cyclictest0-21swapper00:10:150
17745991240616,622cyclictest0-21swapper21:43:420
17745991240616,622cyclictest0-21swapper21:38:010
17745991240616,622cyclictest0-21swapper00:04:330
17745991238611,625cyclictest0-21swapper23:31:440
17745991234610,622cyclictest0-21swapper21:11:530
17745991233611,620cyclictest0-21swapper19:35:560
17745991233604,627cyclictest0-21swapper22:54:330
17745991231604,625cyclictest0-21swapper19:58:320
17745991231604,625cyclictest0-21swapper19:34:450
17745991230606,622cyclictest0-21swapper22:17:320
17745991229603,624cyclictest0-21swapper20:43:350
17745991228603,623cyclictest0-21swapper23:16:490
17745991228602,624cyclictest0-21swapper21:00:300
17745991228602,624cyclictest0-21swapper20:00:230
17745991227609,616cyclictest0-21swapper22:43:500
17745991227601,624cyclictest0-21swapper20:11:460
17745991224607,615cyclictest0-21swapper21:28:280
17745991222599,621cyclictest0-21swapper21:17:350
17745991222599,621cyclictest0-21swapper19:15:100
17745991220599,619cyclictest0-21swapper19:51:200
17745991220597,621cyclictest0-21swapper22:04:280
17745991219598,619cyclictest0-21swapper00:36:520
17745991215585,628cyclictest0-21swapper20:28:310
17745991214588,624cyclictest0-21swapper23:50:090
17745991214588,624cyclictest0-21swapper23:23:110
17745991209582,625cyclictest0-21swapper19:40:470
17745991205583,620cyclictest0-21swapper23:08:070
17745991205579,624cyclictest0-21swapper00:16:370
17745991203581,620cyclictest0-21swapper20:35:030
17745991203578,623cyclictest0-21swapper23:29:430
17745991201580,619cyclictest0-21swapper20:30:410
17745991191560,629cyclictest0-21swapper00:22:580
17745991184558,624cyclictest0-21swapper22:26:050
17745991171543,626cyclictest0-21swapper23:36:050
17745991158530,626cyclictest0-21swapper22:31:460
17745991157533,622cyclictest0-21swapper21:20:160
17745991157530,625cyclictest0-21swapper20:19:080
17745991156529,625cyclictest0-21swapper21:45:130
17745991154524,628cyclictest0-21swapper19:21:320
17745991145518,625cyclictest0-21swapper21:09:430
17745991132504,626cyclictest0-21swapper22:09:000
17745991130509,619cyclictest0-21swapper20:45:160
17745991127502,623cyclictest0-21swapper20:51:370
17745991122499,621cyclictest0-21swapper22:11:000
17745991118493,623cyclictest0-21swapper23:01:450
17745991113491,620cyclictest0-21swapper23:48:490
17745991108481,625cyclictest0-21swapper19:27:030
17745991092465,625cyclictest0-21swapper20:23:190
17745991091465,624cyclictest0-21swapper23:55:100
17745991085460,623cyclictest0-21swapper22:21:430
17745991083463,618cyclictest0-21swapper00:26:190
17745991073450,621cyclictest0-21swapper22:56:440
17745991037607,427cyclictest3772-21ssh22:36:580
17745991031602,426cyclictest1078-21ntp_states21:50:240
1774599949561,385cyclictest24049-21sh00:32:110
1774599938559,376cyclictest9979-21ssh22:45:300
1774599835504,328cyclictest30773-21crond20:59:000
1774599800588,209cyclictest31031-21ssh23:13:580
1774599643618,23cyclictest0-21swapper23:42:570
17745996378,627cyclictest0-21swapper20:07:450
1754627251,17sleep00-21swapper19:09:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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