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2022-01-17 - 01:27

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the alll highest latencies:
System rack6slot6.osadl.org (updated Sun Jan 16, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294059942142462,1750cyclictest2582-21devkit-power-da11:07:020
294059928341572,1259cyclictest1724-21hald12:09:300
294059925832574,7cyclictest1724-21hald09:16:000
29405991251621,628cyclictest0-21swapper09:21:410
29405991248619,627cyclictest0-21swapper07:20:160
29405991245620,624cyclictest0-21swapper11:14:440
29405991243616,625cyclictest0-21swapper11:21:160
29405991241613,626cyclictest0-21swapper10:22:390
29405991240615,623cyclictest0-21swapper08:16:420
29405991240613,625cyclictest0-21swapper08:36:480
29405991238611,625cyclictest0-21swapper07:39:120
29405991238610,626cyclictest0-21swapper07:18:160
29405991238607,629cyclictest0-21swapper11:33:390
29405991237606,629cyclictest0-21swapper07:45:440
29405991236611,623cyclictest0-21swapper12:21:430
29405991236609,625cyclictest0-21swapper11:47:130
29405991235601,632cyclictest0-21swapper11:17:040
29405991230607,621cyclictest0-21swapper10:01:020
29405991227598,627cyclictest0-21swapper10:06:440
29405991225597,626cyclictest0-21swapper12:39:280
29405991224600,622cyclictest0-21swapper09:45:480
29405991224594,628cyclictest0-21swapper12:01:270
29405991221598,621cyclictest0-21swapper07:11:140
29405991220588,630cyclictest0-21swapper09:52:200
29405991219591,626cyclictest0-21swapper11:02:500
29405991217597,618cyclictest0-21swapper08:52:430
29405991215583,630cyclictest0-21swapper10:10:450
29405991213588,623cyclictest0-21swapper08:55:540
29405991213582,629cyclictest0-21swapper12:14:010
29405991211585,624cyclictest0-21swapper08:03:290
29405991207576,629cyclictest0-21swapper10:16:370
29405991206584,620cyclictest0-21swapper09:27:330
29405991203575,626cyclictest0-21swapper07:54:260
29405991199576,621cyclictest0-21swapper09:32:540
29405991196566,628cyclictest0-21swapper10:36:430
29405991185562,621cyclictest0-21swapper08:28:160
29405991180554,624cyclictest0-21swapper10:51:370
29405991178557,619cyclictest0-21swapper07:41:020
29405991176553,621cyclictest0-21swapper09:09:480
29405991176550,624cyclictest0-21swapper07:55:460
29405991165537,626cyclictest0-21swapper08:24:550
29405991165536,627cyclictest0-21swapper09:13:090
29405991164544,618cyclictest0-21swapper12:29:150
29405991161535,624cyclictest0-21swapper10:27:100
29405991160538,620cyclictest0-21swapper09:41:170
29405991158541,615cyclictest0-21swapper09:02:560
29405991151526,623cyclictest0-21swapper11:57:060
29405991151526,623cyclictest0-21swapper08:46:010
29405991146522,622cyclictest0-21swapper09:39:560
29405991141515,624cyclictest0-21swapper08:30:060
29405991138514,622cyclictest0-21swapper08:08:500
29405991137511,624cyclictest0-21swapper12:30:560
29405991137506,629cyclictest0-21swapper09:55:510
29405991129507,620cyclictest0-21swapper10:44:350
29405991119495,622cyclictest0-21swapper10:33:020
29405991104478,624cyclictest0-21swapper07:29:090
29405991102470,630cyclictest0-21swapper08:42:400
29405991099475,622cyclictest0-21swapper07:32:300
29405991087459,626cyclictest0-21swapper11:43:220
29405991086597,485cyclictest654-21ssh10:56:280
29405991084457,625cyclictest0-21swapper11:37:200
29405991060587,470cyclictest11637-21sh11:51:540
2940599983548,433cyclictest31471-21ssh12:17:220
2940599974534,437cyclictest23765-21ssh11:25:470
2940599967540,424cyclictest26939-21ssh10:49:160
2940599814462,349cyclictest2582-21devkit-power-da08:13:320
2731827152,13sleep00-21swapper07:05:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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