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2021-08-05 - 05:51

Intel(R) Celeron(R) M processor 1.60GHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the alll highest latencies:
System rack6slot6.osadl.org (updated Thu Aug 05, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8331991249620,628cyclictest0-21swapper22:10:490
8331991243613,628cyclictest0-21swapper23:39:350
8331991242614,626cyclictest0-21swapper00:30:190
8331991241598,15cyclictest0-21swapper22:29:340
8331991238619,616cyclictest5721-21ssh22:42:180
8331991238611,625cyclictest0-21swapper19:11:570
8331991237612,623cyclictest0-21swapper22:09:180
8331991237611,624cyclictest0-21swapper23:50:580
8331991237607,628cyclictest0-21swapper19:25:010
8331991234605,627cyclictest0-21swapper21:06:200
8331991234601,631cyclictest0-21swapper23:40:550
8331991232607,623cyclictest0-21swapper20:11:350
8331991230623,603cyclictest7761-21ls20:25:190
8331991230610,618cyclictest0-21swapper19:16:490
8331991229606,621cyclictest0-21swapper19:23:110
8331991229603,624cyclictest0-21swapper20:01:420
8331991227606,619cyclictest0-21swapper19:38:050
8331991227602,623cyclictest0-21swapper21:25:460
8331991227602,623cyclictest0-21swapper19:40:560
8331991226601,623cyclictest0-21swapper22:51:510
8331991225605,618cyclictest0-21swapper19:47:480
8331991225602,621cyclictest0-21swapper20:47:150
8331991224596,626cyclictest0-21swapper22:48:500
8331991223599,622cyclictest0-21swapper21:03:300
8331991221599,620cyclictest0-21swapper20:50:060
8331991220594,624cyclictest0-21swapper21:32:280
8331991216607,606cyclictest26247-21taskset19:51:390
8331991216589,625cyclictest0-21swapper20:36:320
8331991213590,621cyclictest0-21swapper22:01:560
8331991212587,623cyclictest0-21swapper23:49:370
8331991211581,628cyclictest0-21swapper20:55:370
8331991209615,591cyclictest2736-21ssh00:35:510
8331991205613,590cyclictest25929-21ssh21:10:110
8331991205578,625cyclictest0-21swapper20:44:140
8331991204599,601cyclictest3835-21ssh21:21:350
8331991204583,619cyclictest0-21swapper22:33:560
8331991197609,585cyclictest5618-21iostat_ios20:20:170
8331991187563,622cyclictest0-21swapper22:36:460
8331991187563,622cyclictest0-21swapper19:56:300
8331991183563,618cyclictest0-21swapper22:24:130
8331991181555,624cyclictest0-21swapper23:05:150
8331991179555,622cyclictest0-21swapper23:00:430
8331991179554,623cyclictest0-21swapper21:50:430
8331991172547,623cyclictest0-21swapper20:17:060
8331991153534,617cyclictest0-21swapper22:17:410
8331991149523,624cyclictest0-21swapper00:06:520
8331991146526,618cyclictest0-21swapper21:15:330
8331991146523,621cyclictest0-21swapper00:03:310
8331991146512,632cyclictest0-21swapper21:35:290
8331991141517,622cyclictest0-21swapper20:32:210
8331991140516,622cyclictest0-21swapper20:07:130
8331991139515,622cyclictest0-21swapper22:59:430
8331991136513,621cyclictest0-21swapper21:55:040
8331991131499,630cyclictest0-21swapper23:16:080
8331991129506,621cyclictest0-21swapper23:24:100
8331991128498,628cyclictest0-21swapper21:45:520
8331991119498,619cyclictest0-21swapper23:58:500
8331991103475,626cyclictest0-21swapper23:12:470
8331991098472,624cyclictest0-21swapper00:22:170
8331991096468,626cyclictest0-21swapper00:13:240
8331991058540,516cyclictest20964-21ssh21:42:310
8331991012615,393cyclictest28644-21sh00:28:590
833199983492,488cyclictest13650-21sshd23:30:520
833199970497,470cyclictest10940-21ssh23:28:110
833199633609,21cyclictest17442-21perl00:15:150
833199632615,16cyclictest0-21swapper19:33:240
760127251,17sleep00-21swapper19:06:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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