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2022-07-02 - 09:34

x86 Intel Celeron M @1600 MHz, Linux 5.4.74-rt41 (Profile)

Latency plot of system in rack #6, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the alll highest latencies:
System rack6slot6.osadl.org (updated Sat Jul 02, 2022 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13646991250617,631cyclictest0-21swapper19:25:400
13646991249620,627cyclictest0-21swapper21:06:590
13646991245614,629cyclictest0-21swapper19:17:270
13646991244619,623cyclictest0-21swapper20:26:270
13646991244617,625cyclictest0-21swapper22:13:380
13646991244614,628cyclictest0-21swapper21:47:210
13646991240616,622cyclictest0-21swapper22:08:270
13646991240615,623cyclictest0-21swapper23:06:530
13646991239616,621cyclictest0-21swapper20:49:540
13646991238612,624cyclictest0-21swapper20:54:150
13646991237614,621cyclictest0-21swapper21:43:090
13646991237613,622cyclictest0-21swapper20:17:150
13646991234608,624cyclictest0-21swapper21:21:530
13646991234601,631cyclictest0-21swapper00:28:470
13646991233612,619cyclictest0-21swapper23:24:180
13646991233612,619cyclictest0-21swapper21:39:280
13646991232604,626cyclictest0-21swapper19:45:150
13646991231605,624cyclictest0-21swapper22:52:590
13646991229603,624cyclictest0-21swapper19:56:490
13646991225600,623cyclictest0-21swapper19:38:540
13646991224597,625cyclictest0-21swapper21:01:470
13646991224597,625cyclictest0-21swapper00:06:110
13646991223592,629cyclictest0-21swapper22:56:300
13646991221592,627cyclictest0-21swapper23:42:340
13646991220598,620cyclictest0-21swapper21:16:420
13646991220595,623cyclictest0-21swapper20:05:310
13646991220590,628cyclictest0-21swapper21:27:450
13646991219598,619cyclictest0-21swapper19:54:380
13646991219597,620cyclictest0-21swapper20:03:210
13646991217590,625cyclictest0-21swapper20:41:110
13646991215587,626cyclictest0-21swapper23:16:260
13646991211590,619cyclictest0-21swapper00:02:500
13646991211586,623cyclictest0-21swapper23:46:550
13646991211582,627cyclictest0-21swapper19:11:260
13646991210586,622cyclictest0-21swapper22:31:030
13646991209585,622cyclictest0-21swapper19:22:090
13646991208581,625cyclictest0-21swapper19:43:450
13646991205575,628cyclictest0-21swapper00:24:560
13646991204578,624cyclictest0-21swapper23:39:030
13646991200573,625cyclictest0-21swapper20:32:390
13646991196570,624cyclictest0-21swapper22:39:150
13646991195562,631cyclictest0-21swapper22:17:390
13646991194574,618cyclictest0-21swapper22:27:320
13646991190565,623cyclictest0-21swapper00:18:540
13646991189568,619cyclictest0-21swapper23:31:100
13646991184561,621cyclictest0-21swapper21:50:310
13646991183564,617cyclictest0-21swapper00:35:090
13646991181555,624cyclictest0-21swapper23:58:180
13646991179555,622cyclictest0-21swapper21:33:270
13646991173549,622cyclictest0-21swapper00:32:580
13646991171542,627cyclictest0-21swapper19:33:020
13646991168546,620cyclictest0-21swapper20:58:260
13646991165536,627cyclictest0-21swapper22:24:010
13646991152525,625cyclictest0-21swapper23:14:360
13646991148522,624cyclictest0-21swapper20:10:230
13646991140512,626cyclictest0-21swapper21:11:500
13646991139512,625cyclictest0-21swapper22:02:050
13646991137510,625cyclictest0-21swapper23:53:170
13646991133508,623cyclictest0-21swapper20:24:370
13646991127510,615cyclictest0-21swapper23:25:490
13646991121494,625cyclictest0-21swapper21:59:540
13646991120600,517cyclictest7920-21irqstats22:45:170
13646991112487,623cyclictest0-21swapper20:37:500
13646991095589,504cyclictest6688-21ssh22:44:070
13646991095467,626cyclictest0-21swapper23:02:120
1364699937610,324cyclictest9842-21ssh00:10:420
1335026756,6sleep00-21swapper19:09:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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