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2022-10-05 - 04:06

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the highest latencies:
System rack6slot7.osadl.org (updated Wed Oct 05, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
970721030,0sleep10-21swapper/122:04:321
1736421000,1sleep117365-21processes21:36:341
73022780,0sleep07305-21head22:36:360
73022780,0sleep07305-21head22:36:360
30138997056,12cyclictest9455-21kworker/u4:023:24:210
30138996958,10cyclictest9099-21ssh21:27:180
125912690,1sleep112592-21sh23:55:191
30138996858,9cyclictest0-21swapper/023:26:170
30138996858,9cyclictest0-21swapper/021:59:180
30138996858,9cyclictest0-21swapper/021:53:170
30138996858,9cyclictest0-21swapper/021:48:190
30138996858,9cyclictest0-21swapper/021:32:190
30138996858,9cyclictest0-21swapper/020:59:180
30138996858,9cyclictest0-21swapper/020:36:180
30138996858,9cyclictest0-21swapper/019:41:180
30138996858,9cyclictest0-21swapper/000:07:170
21852680,7sleep03013899cyclictest23:06:500
30138996758,8cyclictest0-21swapper/019:34:210
30138996757,9cyclictest0-21swapper/023:05:170
30138996757,9cyclictest0-21swapper/022:11:170
30138996757,9cyclictest0-21swapper/021:04:180
30138996757,9cyclictest0-21swapper/020:50:180
3013899674,61cyclictest1308-21dbus-daemon20:23:210
3013899673,62cyclictest1609-21lldpd21:16:180
30143996662,3cyclictest0-21swapper/121:47:181
30143996661,4cyclictest0-21swapper/121:03:211
3014399664,61cyclictest0-21swapper/123:48:171
3014399664,61cyclictest0-21swapper/122:21:181
3014399664,61cyclictest0-21swapper/122:10:181
3014399664,60cyclictest23116-21sh22:19:181
3014399663,62cyclictest0-21swapper/123:36:201
3014399663,62cyclictest0-21swapper/123:35:181
3014399663,62cyclictest0-21swapper/121:42:211
3014399662,63cyclictest0-21swapper/121:17:201
30138996657,8cyclictest0-21swapper/022:44:170
30138996656,9cyclictest0-21swapper/022:32:180
30138996643,21cyclictest16518-21diskmemload00:22:200
3013899663,62cyclictest0-21swapper/021:22:180
30143996561,3cyclictest0-21swapper/123:02:181
30143996561,3cyclictest0-21swapper/122:57:171
30143996561,3cyclictest0-21swapper/122:51:191
30143996561,3cyclictest0-21swapper/122:43:181
30143996561,3cyclictest0-21swapper/121:29:181
30143996561,3cyclictest0-21swapper/120:58:191
30143996561,3cyclictest0-21swapper/120:43:201
30143996561,3cyclictest0-21swapper/120:24:201
30143996561,3cyclictest0-21swapper/120:08:211
30143996561,3cyclictest0-21swapper/120:00:181
30143996561,3cyclictest0-21swapper/119:31:201
30143996561,3cyclictest0-21swapper/119:26:201
30143996561,3cyclictest0-21swapper/119:21:201
30143996561,3cyclictest0-21swapper/119:09:181
30143996561,3cyclictest0-21swapper/100:26:171
30143996561,3cyclictest0-21swapper/100:15:191
30143996561,3cyclictest0-21swapper/100:06:191
30143996560,4cyclictest0-21swapper/123:56:201
30143996541,23cyclictest0-21swapper/121:06:181
3014399654,60cyclictest0-21swapper/120:18:181
3014399654,60cyclictest0-21swapper/119:54:191
3014399654,60cyclictest0-21swapper/100:21:181
30143996531,33cyclictest0-21swapper/123:22:181
3014399653,61cyclictest0-21swapper/123:43:191
3014399653,61cyclictest0-21swapper/123:26:191
3014399653,61cyclictest0-21swapper/123:14:171
3014399653,61cyclictest0-21swapper/123:08:181
3014399653,61cyclictest0-21swapper/122:47:181
3014399653,61cyclictest0-21swapper/122:36:181
3014399653,61cyclictest0-21swapper/122:36:181
3014399653,61cyclictest0-21swapper/122:33:201
3014399653,61cyclictest0-21swapper/122:28:191
3014399653,61cyclictest0-21swapper/121:51:191
3014399653,61cyclictest0-21swapper/121:31:181
3014399653,61cyclictest0-21swapper/121:23:191
3014399653,61cyclictest0-21swapper/121:14:181
3014399653,61cyclictest0-21swapper/120:01:201
3013899654,60cyclictest0-21swapper/021:44:200
3013899654,60cyclictest0-21swapper/019:24:190
3013899653,61cyclictest0-21swapper/023:19:190
3013899653,61cyclictest0-21swapper/019:20:190
30143996460,3cyclictest0-21swapper/121:56:171
30143996460,3cyclictest0-21swapper/120:55:211
30143996441,22cyclictest0-21swapper/119:01:181
30143996441,22cyclictest0-21swapper/100:02:181
30143996432,30cyclictest12673-21ssh23:19:181
3014399643,60cyclictest0-21swapper/122:11:201
30138996460,3cyclictest0-21swapper/020:16:200
30138996459,4cyclictest0-21swapper/021:15:180
30138996458,5cyclictest1308-21dbus-daemon23:51:210
3013899643,60cyclictest0-21swapper/020:14:210
3013899643,60cyclictest0-21swapper/019:27:210
3013899643,60cyclictest0-21swapper/019:05:210
30143996341,21cyclictest0-21swapper/120:36:181
30143996341,21cyclictest0-21swapper/120:33:201
30143996341,21cyclictest0-21swapper/119:46:201
30143996341,21cyclictest0-21swapper/119:43:211
30143996341,21cyclictest0-21swapper/119:36:211
30143996331,31cyclictest0-21swapper/120:46:181
30143996331,31cyclictest0-21swapper/120:26:211
30143996331,31cyclictest0-21swapper/120:12:191
30143996331,31cyclictest0-21swapper/119:17:211
30143996331,31cyclictest0-21swapper/119:11:211
30143996321,41cyclictest0-21swapper/100:16:181
30138996359,3cyclictest0-21swapper/000:01:190
30138996358,4cyclictest0-21swapper/023:58:170
30138996358,4cyclictest0-21swapper/022:19:200
30138996358,4cyclictest0-21swapper/021:37:170
30138996358,4cyclictest0-21swapper/020:43:190
30138996357,4cyclictest16518-21diskmemload21:06:210
30138996354,8cyclictest26505-21kworker/u4:120:04:190
30138996341,21cyclictest0-21swapper/019:08:210
270712631,60sleep00-21swapper/022:23:180
30138996260,1cyclictest5696-21kworker/u4:022:51:180
30138996258,3cyclictest0-21swapper/023:50:170
30138996258,3cyclictest0-21swapper/000:13:180
30138996157,3cyclictest0-21swapper/020:35:180
30138996157,3cyclictest0-21swapper/020:07:200
30138996157,3cyclictest0-21swapper/019:51:210
30138995854,3cyclictest31294-21ssh23:40:170
30138995755,1cyclictest26505-21kworker/u4:119:50:200
30138995755,1cyclictest26505-21kworker/u4:119:37:200
30138995755,1cyclictest26505-21kworker/u4:119:14:220
30138995755,1cyclictest11459-21kworker/u4:200:16:190
30138995753,3cyclictest0-21swapper/023:15:190
30138995654,1cyclictest9901-21kworker/u4:220:53:190
30138995654,1cyclictest26505-21kworker/u4:120:27:180
30138995654,1cyclictest12256-21kworker/u4:022:02:210
30138995652,3cyclictest16785-21ssh22:47:170
30138995652,3cyclictest0-21swapper/023:33:180
30138995553,1cyclictest10175-21kworker/u4:222:07:180
3013899553,51cyclictest31025-21ssh22:27:180
30138995349,3cyclictest26979-21ssh22:59:210
30138995347,4cyclictest11875-21ssh00:30:200
30138994946,2cyclictest0-21swapper/023:44:180
2977223314,3sleep00-21swapper/018:58:400
3013899301,24cyclictest22196-21date19:56:270
2993823015,12sleep10-21swapper/119:00:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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