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2023-10-01 - 01:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot7.osadl.org (updated Sat Sep 30, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
379221130,0sleep13794-21proc_pri09:44:331
231872850,1sleep00-21swapper/007:14:320
1991099702,67cyclictest0-21swapper/107:25:161
1990999696,61cyclictest1279-21dbus-daemon09:39:180
1990999694,63cyclictest1305-21wpa_supplicant10:46:180
19909996862,4cyclictest1279-21dbus-daemon10:02:180
1990999684,62cyclictest1289-21NetworkManager11:45:180
19910996757,9cyclictest0-21swapper/110:02:141
1990999674,61cyclictest1289-21NetworkManager12:24:180
1990999674,61cyclictest1289-21NetworkManager12:11:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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