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2023-02-08 - 05:21

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot7.osadl.org (updated Wed Feb 08, 2023 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262002870,0sleep00-21swapper/022:50:210
254582780,0sleep00-21swapper/020:36:410
23522740,1sleep12355-21gltestperf00:16:361
260202700,1sleep10-21swapper/123:27:361
22711996756,10cyclictest22170-21ssh21:27:321
22706996762,4cyclictest22701-21cyclictest20:22:310
2270699674,61cyclictest0-21swapper/000:10:280
22706996661,4cyclictest0-21swapper/023:10:280
22706996661,4cyclictest0-21swapper/022:12:290
22706996661,4cyclictest0-21swapper/019:57:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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