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2022-05-29 - 14:07

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot7.osadl.org (updated Sun May 29, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8902830,0sleep10-21swapper/100:15:561
11422997757,18cyclictest4254-21sh23:08:420
11422997452,21cyclictest0-21swapper/021:53:420
11422997442,31cyclictest0-21swapper/000:42:450
11422997432,41cyclictest0-21swapper/000:03:420
11422997332,40cyclictest0-21swapper/023:26:420
11422997332,40cyclictest0-21swapper/023:11:420
1142299733,69cyclictest0-21swapper/022:39:420
11422997323,49cyclictest0-21swapper/022:12:420
11422997322,50cyclictest0-21swapper/023:51:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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