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2021-06-17 - 18:29

Pentium(R) Dual-Core CPU T4500 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot7.osadl.org (updated Thu Jun 17, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285632790,6sleep02107399cyclictest11:45:020
2108199665,60cyclictest21066-21cyclictest10:59:111
2108199664,61cyclictest1655-21ssh11:54:091
2108199663,62cyclictest0-21swapper/111:38:101
2108199663,62cyclictest0-21swapper/110:50:091
2107399661,64cyclictest0-21swapper/008:35:110
21081996562,2cyclictest7418-21kworker/u4:007:53:071
2108199653,61cyclictest0-21swapper/111:33:091
2108199653,61cyclictest0-21swapper/109:21:111
2108199653,61cyclictest0-21swapper/109:14:081
2108199652,62cyclictest0-21swapper/112:28:091
2108199652,62cyclictest0-21swapper/108:51:071
2108199652,62cyclictest0-21swapper/108:10:101
21081996461,2cyclictest24173-21kworker/u4:009:41:101
21081996461,2cyclictest18343-21kworker/u4:012:12:081
2108199643,60cyclictest0-21swapper/110:30:101
2108199643,60cyclictest0-21swapper/110:12:101
2108199643,60cyclictest0-21swapper/110:07:091
2108199642,61cyclictest0-21swapper/108:47:101
2107399641,62cyclictest0-21swapper/009:09:100
2107399641,62cyclictest0-21swapper/007:57:100
2107399641,62cyclictest0-21swapper/007:21:100
21081996361,1cyclictest7418-21kworker/u4:007:57:071
21081996361,1cyclictest4225-21kworker/u4:211:15:071
21081996360,2cyclictest24324-21kworker/u4:011:01:071
2108199632,60cyclictest0-21swapper/112:22:081
21081996260,1cyclictest22257-21kworker/u4:108:38:091
21081996260,1cyclictest18343-21kworker/u4:012:18:081
21081996257,4cyclictest24869-21kworker/u4:207:17:111
21081996257,2cyclictest0-21swapper/111:56:101
21073996159,1cyclictest22498-21kworker/u4:211:41:110
21073996159,1cyclictest18343-21kworker/u4:011:38:090
21073996158,2cyclictest24324-21kworker/u4:011:04:090
2107399611,58cyclictest1605-21snmpd12:03:110
65802600,4sleep02107399cyclictest11:15:540
2107399601,58cyclictest0-21swapper/008:56:100
2107399601,57cyclictest1747-21runrttasks07:54:100
2107399591,57cyclictest0-21swapper/009:46:090
2107399591,57cyclictest0-21swapper/008:52:080
2107399591,57cyclictest0-21swapper/008:43:100
2107399591,57cyclictest0-21swapper/008:27:100
2107399591,57cyclictest0-21swapper/008:19:090
2107399591,57cyclictest0-21swapper/007:42:100
21081995856,1cyclictest8011-21kworker/u4:212:07:081
21081995856,1cyclictest28291-21kworker/u4:008:44:081
21081995855,2cyclictest0-21swapper/110:24:101
21073995855,2cyclictest16431-21kworker/u4:210:50:090
21073995854,3cyclictest20175-21kworker/u4:309:28:090
2107399581,55cyclictest1316-21dbus-daemon12:34:110
21081995755,1cyclictest16611-21kworker/u4:107:26:071
21081995755,1cyclictest15660-21kworker/u4:208:15:091
21081995754,2cyclictest0-21swapper/109:55:101
21073995755,1cyclictest20306-21kworker/u4:110:59:110
21073995754,2cyclictest30445-21kworker/u4:108:49:090
21073995754,2cyclictest22498-21kworker/u4:211:52:080
21073995754,2cyclictest18489-21kworker/u4:010:10:110
2107399571,55cyclictest0-21swapper/007:45:090
21081995654,1cyclictest5217-21kworker/u4:207:48:081
21081995654,1cyclictest32378-21kworker/u4:111:13:081
21081995654,1cyclictest22678-21kworker/u4:007:13:091
21081995654,1cyclictest22257-21kworker/u4:108:33:091
21081995654,1cyclictest0-21swapper/109:30:101
21073995654,1cyclictest7418-21kworker/u4:008:10:100
21073995654,1cyclictest6914-21kworker/u4:209:21:110
21073995654,1cyclictest6914-21kworker/u4:209:14:080
21073995654,1cyclictest2848-21kworker/u4:210:30:100
21073995653,2cyclictest2848-21kworker/u4:210:35:090
21073995653,2cyclictest16356-21kworker/u4:212:17:090
2108199553,51cyclictest0-21swapper/109:28:091
21073995554,1cyclictest16356-21kworker/u4:212:28:090
21073995553,1cyclictest4180-21kworker/u4:209:51:100
21073995553,1cyclictest32378-21kworker/u4:111:33:090
21073995553,1cyclictest24324-21kworker/u4:011:06:080
21073995553,1cyclictest18489-21kworker/u4:010:07:090
21073995553,1cyclictest16356-21kworker/u4:212:22:080
2107399554,50cyclictest0-21swapper/011:10:110
2107399551,53cyclictest0-21swapper/009:40:080
2107399551,53cyclictest0-21swapper/007:31:100
2107399541,52cyclictest0-21swapper/010:44:070
2107399541,52cyclictest0-21swapper/007:38:080
21081995351,1cyclictest26630-21kworker/u4:111:45:071
21081995351,1cyclictest24456-21kworker/u4:208:55:071
21081995351,1cyclictest0-21swapper/107:24:091
21073995351,1cyclictest6914-21kworker/u4:209:17:070
21073995350,2cyclictest0-21swapper/012:12:080
21081995249,2cyclictest0-21swapper/111:42:081
21081995231,20cyclictest0-21swapper/109:05:091
21081995149,1cyclictest0-21swapper/108:03:091
21081995148,2cyclictest0-21swapper/111:29:101
21081995048,1cyclictest0-21swapper/112:39:091
21081995048,1cyclictest0-21swapper/110:26:081
21081994947,1cyclictest0-21swapper/111:06:091
21081994947,1cyclictest0-21swapper/110:04:091
21081994947,1cyclictest0-21swapper/108:29:101
21073994947,1cyclictest3837-21kworker/u4:111:56:100
2107399491,47cyclictest0-21swapper/010:15:080
2107399491,47cyclictest0-21swapper/008:30:090
2107399491,47cyclictest0-21swapper/007:11:080
2107399481,46cyclictest0-21swapper/007:25:090
21073994745,1cyclictest26977-21kworker/u4:110:24:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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