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2022-05-26 - 21:52

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot7.osadl.org (updated Fri May 20, 2022 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217722750,1sleep00-21swapper/021:54:350
269199675,61cyclictest0-21swapper/023:36:500
2691996660,4cyclictest1305-21dbus-daemon20:06:500
2691996651,13cyclictest1749-21runrttasks21:09:480
269199663,62cyclictest0-21swapper/023:33:470
270199653,61cyclictest0-21swapper/122:23:471
2691996561,3cyclictest0-21swapper/022:12:480
2691996552,11cyclictest1305-21dbus-daemon19:55:500
269199653,60cyclictest1305-21dbus-daemon23:41:510
2701996462,1cyclictest2259-21kworker/u4:119:17:491
2701996462,1cyclictest2259-21kworker/u4:119:17:491
2701996461,2cyclictest905-21kworker/u4:100:29:501
2691996460,3cyclictest0-21swapper/023:53:500
2691996460,3cyclictest0-21swapper/022:46:490
2691996460,3cyclictest0-21swapper/022:21:510
2691996460,3cyclictest0-21swapper/021:37:500
2691996458,5cyclictest0-21swapper/020:56:480
2691996458,5cyclictest0-21swapper/000:41:480
2691996451,11cyclictest1749-21runrttasks20:34:480
269199643,59cyclictest21402-21diskmemload22:42:500
2691996413,50cyclictest0-21swapper/021:06:500
2701996361,1cyclictest17174-21kworker/u4:119:47:481
2701996361,1cyclictest14583-21kworker/u4:120:56:501
2701996361,1cyclictest13765-21kworker/u4:123:16:491
2701996361,1cyclictest1306-21kworker/u4:300:00:491
2701996360,2cyclictest0-21swapper/121:42:501
2701996312,50cyclictest0-21swapper/121:33:501
2691996361,1cyclictest8393-21kworker/u4:120:44:480
2691996359,3cyclictest0-21swapper/023:07:480
2691996359,3cyclictest0-21swapper/022:57:480
2691996359,3cyclictest0-21swapper/022:24:470
2691996359,3cyclictest0-21swapper/021:20:470
2691996359,3cyclictest0-21swapper/019:49:490
2691996359,3cyclictest0-21swapper/019:32:490
2691996359,3cyclictest0-21swapper/019:27:480
2691996358,4cyclictest0-21swapper/020:22:500
2691996358,4cyclictest0-21swapper/019:38:490
2691996341,21cyclictest0-21swapper/021:41:500
2691996331,31cyclictest0-21swapper/021:59:490
269199633,59cyclictest19515-21ssh22:33:480
2691996322,40cyclictest0-21swapper/000:06:500
2701996260,1cyclictest22650-21kworker/u4:023:21:471
2701996260,1cyclictest2259-21kworker/u4:119:28:481
2701996260,1cyclictest12857-21kworker/u4:019:37:491
2701996259,2cyclictest19034-21kworker/u4:021:28:491
2701996258,2cyclictest30961-21kworker/u4:322:09:511
2701996241,20cyclictest0-21swapper/120:04:491
2691996258,3cyclictest0-21swapper/021:16:500
2691996258,3cyclictest0-21swapper/020:41:490
2691996258,3cyclictest0-21swapper/020:27:490
2691996258,3cyclictest0-21swapper/020:16:490
2691996258,3cyclictest0-21swapper/019:40:480
2691996258,3cyclictest0-21swapper/019:16:470
2691996258,3cyclictest0-21swapper/019:16:470
2691996257,4cyclictest0-21swapper/021:53:480
2691996257,4cyclictest0-21swapper/021:27:500
2691996257,4cyclictest0-21swapper/020:31:480
2691996257,4cyclictest0-21swapper/019:23:480
202052620,1sleep00-21swapper/023:54:350
2701996159,1cyclictest20966-21kworker/u4:200:37:481
2701996159,1cyclictest10702-21kworker/u4:219:54:501
2701996158,2cyclictest3951-21kworker/u4:220:41:491
2701996158,2cyclictest30140-21kworker/u4:022:59:481
2701996157,2cyclictest2909-21kworker/u4:121:44:471
2691996157,3cyclictest0-21swapper/023:19:500
2691996157,3cyclictest0-21swapper/021:29:480
2691996157,3cyclictest0-21swapper/020:59:500
2691996157,3cyclictest0-21swapper/020:49:500
2691996157,3cyclictest0-21swapper/020:09:490
2691996157,3cyclictest0-21swapper/020:00:490
2691996157,3cyclictest0-21swapper/000:37:480
2691996157,3cyclictest0-21swapper/000:22:490
2691996157,3cyclictest0-21swapper/000:15:480
2691996156,4cyclictest0-21swapper/019:44:480
269199610,60cyclictest0-21swapper/021:44:510
2701996058,1cyclictest5296-21kworker/u4:200:18:471
2691996056,3cyclictest0-21swapper/023:01:480
2701995957,1cyclictest15860-21kworker/u4:021:55:491
2701995957,1cyclictest11478-21kworker/u4:222:28:501
2701995956,2cyclictest0-21swapper/121:17:471
2691995957,1cyclictest0-21swapper/023:13:500
2701995857,1cyclictest14583-21kworker/u4:121:12:491
2701995856,1cyclictest21667-21kworker/u4:122:43:491
2701995856,1cyclictest15505-21kworker/u4:022:31:501
2701995856,1cyclictest10614-21kworker/u4:020:52:471
2701995856,1cyclictest0-21swapper/100:42:481
2701995855,2cyclictest21667-21kworker/u4:122:37:511
2691995856,1cyclictest905-21kworker/u4:100:26:480
2691995856,1cyclictest27701-21kworker/u4:122:04:480
2691995856,1cyclictest1306-21kworker/u4:300:00:500
2701995755,1cyclictest2909-21kworker/u4:121:50:481
2701995755,1cyclictest22650-21kworker/u4:023:31:491
2701995755,1cyclictest21667-21kworker/u4:122:56:501
2701995755,1cyclictest21667-21kworker/u4:122:53:471
2701995755,1cyclictest19034-21kworker/u4:021:20:481
2701995755,1cyclictest14583-21kworker/u4:121:00:481
2701995755,1cyclictest1397-21ssh00:11:481
2701995755,1cyclictest0-21swapper/123:08:501
2701995755,1cyclictest0-21swapper/100:24:481
2691995755,1cyclictest5829-21kworker/u4:122:16:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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