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2022-09-25 - 12:19
/usr/bin/Xorg /usr/bin/Xorg

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot7.osadl.org (updated Sun Sep 25, 2022 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
284792840,1sleep00-21swapper/021:52:250
2005996661,4cyclictest17457-21munin-node22:17:311
1998996655,10cyclictest3313-21kworker/u4:323:37:300
199899664,61cyclictest0-21swapper/019:15:320
199899664,61cyclictest0-21swapper/000:29:330
199899663,62cyclictest12313-21ls23:32:330
199899663,62cyclictest0-21swapper/023:15:310
2287226556,7sleep121961-21kworker/u4:022:25:321
2005996559,4cyclictest10495-21munin-node00:12:331
1998996555,9cyclictest18397-21kworker/u4:023:51:310
1998996554,10cyclictest16547-21kworker/u4:119:51:310
1998996553,11cyclictest0-21swapper/019:28:330
1998996513,50cyclictest20780-21diskmemload21:24:340
2005996460,3cyclictest133150irq/30-eth021:17:321
2005996459,4cyclictest0-21swapper/121:44:321
200599644,59cyclictest0-21swapper/120:37:311
2005996432,31cyclictest0-21swapper/119:10:321
200599643,60cyclictest0-21swapper/123:54:331
200599643,60cyclictest0-21swapper/122:08:331
2005996423,40cyclictest0-21swapper/123:36:321
2005996422,41cyclictest0-21swapper/121:00:311
1998996458,4cyclictest1318-21NetworkManager23:57:340
1998996454,9cyclictest3313-21kworker/u4:323:22:330
1998996454,9cyclictest20533-21kworker/u4:221:02:310
1998996454,9cyclictest11835-21kworker/u4:200:14:300
1998996454,9cyclictest10276-21kworker/u4:021:33:340
199899643,60cyclictest0-21swapper/019:36:330
2005996361,1cyclictest32443-21kworker/u4:221:32:341
2005996359,3cyclictest22880-21ssh23:06:321
2005996359,3cyclictest0-21swapper/122:13:331
2005996359,3cyclictest0-21swapper/121:03:331
2005996331,31cyclictest0-21swapper/121:48:311
200599632,60cyclictest0-21swapper/123:20:301
2005996312,50cyclictest0-21swapper/123:25:331
2005996312,50cyclictest0-21swapper/120:49:331
2005996312,50cyclictest0-21swapper/119:13:351
1998996358,4cyclictest16638-21ssh22:57:330
2005996260,1cyclictest3313-21kworker/u4:323:38:341
2005996260,1cyclictest20533-21kworker/u4:221:08:331
2005996260,1cyclictest1516-21kworker/u4:219:23:341
2005996258,3cyclictest0-21swapper/123:58:341
2005996258,3cyclictest0-21swapper/120:34:341
2005996257,4cyclictest20346-21ls23:42:321
2005996257,4cyclictest0-21swapper/123:01:311
2005996257,4cyclictest0-21swapper/119:48:331
2005996257,4cyclictest0-21swapper/100:25:311
2005996257,4cyclictest0-21swapper/100:08:311
1998996259,2cyclictest17522-21kworker/u4:322:37:330
1998996256,4cyclictest1308-21dbus-daemon20:29:350
1998996252,9cyclictest0-21swapper/022:21:310
1998996252,9cyclictest0-21swapper/020:17:310
2005996157,3cyclictest0-21swapper/123:08:321
2005996157,3cyclictest0-21swapper/122:55:331
2005996157,3cyclictest0-21swapper/122:48:311
2005996157,3cyclictest0-21swapper/122:03:311
2005996157,3cyclictest0-21swapper/121:39:321
2005996157,3cyclictest0-21swapper/121:13:341
2005996157,3cyclictest0-21swapper/120:43:331
2005996157,3cyclictest0-21swapper/120:27:331
2005996157,3cyclictest0-21swapper/120:13:321
2005996157,3cyclictest0-21swapper/120:07:341
2005996157,3cyclictest0-21swapper/119:53:351
2005996157,3cyclictest0-21swapper/119:37:351
2005996157,3cyclictest0-21swapper/100:29:301
2005996157,3cyclictest0-21swapper/100:21:321
2005996157,3cyclictest0-21swapper/100:04:331
2005996156,4cyclictest10442-21ssh23:31:311
2005996156,4cyclictest0-21swapper/123:48:311
2005996156,4cyclictest0-21swapper/122:27:331
1998996152,8cyclictest0-21swapper/020:01:310
2005996056,3cyclictest0-21swapper/123:14:331
2005996056,3cyclictest0-21swapper/122:43:321
2005996056,3cyclictest0-21swapper/122:33:321
2005996056,3cyclictest0-21swapper/122:01:331
2005996056,3cyclictest0-21swapper/121:53:311
2005996056,3cyclictest0-21swapper/121:29:341
2005996056,3cyclictest0-21swapper/121:22:321
2005996056,3cyclictest0-21swapper/120:56:341
2005996056,3cyclictest0-21swapper/120:22:331
2005996056,3cyclictest0-21swapper/120:17:321
2005996056,3cyclictest0-21swapper/120:02:341
2005996056,3cyclictest0-21swapper/119:57:341
2005996056,3cyclictest0-21swapper/119:43:331
2005996056,3cyclictest0-21swapper/119:32:321
2005996056,3cyclictest0-21swapper/119:27:321
2005996056,3cyclictest0-21swapper/119:17:351
2005996056,3cyclictest0-21swapper/119:02:331
2005996055,4cyclictest0-21swapper/122:40:331
1998996051,8cyclictest0-21swapper/023:56:340
1998996051,8cyclictest0-21swapper/019:25:320
1998995953,4cyclictest22890-21ssh22:25:340
1998995856,1cyclictest6030-21kworker/u4:100:19:320
1998995854,3cyclictest1240-21ls21:57:320
1998995854,3cyclictest0-21swapper/000:25:320
1998995853,4cyclictest0-21swapper/023:28:300
1998995853,3cyclictest20780-21diskmemload22:55:330
1998995847,10cyclictest0-21swapper/021:47:310
1998995755,1cyclictest6787-21kworker/u4:222:47:310
1998995755,1cyclictest29467-21kworker/u4:123:17:310
1998995755,1cyclictest29324-21kworker/u4:220:12:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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