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2021-10-26 - 22:15

Pentium(R) Dual-Core CPU T4500 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot7.osadl.org (updated Tue Oct 26, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325022760,0sleep10-21swapper/110:22:431
2569299732,4cyclictest0-21swapper/107:32:571
170952730,0sleep117096-21sh10:02:251
118612730,0sleep00-21swapper/010:38:070
25692997261,10cyclictest1751-21kworker/u4:211:02:581
25692997059,10cyclictest0-21swapper/112:26:561
25692996960,8cyclictest0-21swapper/109:14:581
25692996859,8cyclictest0-21swapper/110:26:581
25692996859,8cyclictest0-21swapper/109:36:581
25685996861,5cyclictest25218-21yum09:28:560
25692996760,6cyclictest0-21swapper/108:06:561
25692996750,16cyclictest0-21swapper/112:15:571
25692996741,25cyclictest0-21swapper/111:06:551
25692996741,25cyclictest0-21swapper/110:38:551
2568599664,61cyclictest0-21swapper/011:40:570
25692996561,3cyclictest0-21swapper/108:39:561
25692996560,4cyclictest0-21swapper/108:47:551
25692996560,4cyclictest0-21swapper/108:29:561
25692996560,4cyclictest0-21swapper/108:25:551
25692996560,4cyclictest0-21swapper/107:37:551
25692996560,4cyclictest0-21swapper/107:14:571
25685996551,13cyclictest0-21swapper/011:13:560
25685996542,21cyclictest12063-21diskmemload10:03:550
2568599653,61cyclictest0-21swapper/011:37:560
2568599653,61cyclictest0-21swapper/010:55:580
2568599653,60cyclictest12063-21diskmemload11:57:580
25685996523,40cyclictest12063-21diskmemload12:28:580
25685996523,40cyclictest12063-21diskmemload12:01:580
25692996460,3cyclictest0-21swapper/108:20:571
25692996460,3cyclictest0-21swapper/107:56:561
25692996460,3cyclictest0-21swapper/107:51:551
25692996460,3cyclictest0-21swapper/107:40:581
25692996460,3cyclictest0-21swapper/107:25:581
25685996460,3cyclictest0-21swapper/010:30:550
25685996460,3cyclictest0-21swapper/009:05:560
25685996460,3cyclictest0-21swapper/008:10:570
25685996460,3cyclictest0-21swapper/007:43:550
25685996459,4cyclictest0-21swapper/008:38:550
25685996451,12cyclictest0-21swapper/011:01:560
25685996451,12cyclictest0-21swapper/010:08:580
25685996450,13cyclictest0-21swapper/007:58:560
25685996441,21cyclictest19112-21rt-features11:28:570
2568599643,60cyclictest0-21swapper/012:34:580
25692996359,3cyclictest0-21swapper/108:12:571
25692996351,11cyclictest0-21swapper/112:04:551
25692996351,11cyclictest0-21swapper/111:22:571
25692996351,11cyclictest0-21swapper/109:31:561
25692996350,12cyclictest0-21swapper/111:35:551
25692996350,12cyclictest0-21swapper/109:23:571
25692996341,21cyclictest0-21swapper/112:28:571
25692996341,21cyclictest0-21swapper/110:49:581
25692996341,21cyclictest0-21swapper/110:43:581
25692996331,31cyclictest0-21swapper/109:49:581
25685996359,3cyclictest0-21swapper/008:58:560
25685996351,11cyclictest0-21swapper/007:54:550
25685996341,21cyclictest14331-21ssh12:04:550
25685996341,21cyclictest0-21swapper/010:25:570
25685996341,21cyclictest0-21swapper/008:24:550
25685996331,31cyclictest0-21swapper/010:48:580
25685996331,31cyclictest0-21swapper/009:23:570
25685996331,31cyclictest0-21swapper/008:05:560
25685996322,40cyclictest0-21swapper/007:21:570
2568599632,60cyclictest0-21swapper/012:23:570
25685996312,50cyclictest0-21swapper/009:59:560
25692996250,11cyclictest0-21swapper/112:33:571
25692996250,11cyclictest0-21swapper/108:58:541
25692996250,11cyclictest0-21swapper/108:02:561
25692996240,21cyclictest0-21swapper/108:56:551
25685996255,5cyclictest19066-21ssh12:11:560
25685996250,11cyclictest0-21swapper/011:03:560
25685996250,11cyclictest0-21swapper/009:36:570
25685996159,1cyclictest27287-21kworker/u4:008:34:540
25685996157,3cyclictest12063-21diskmemload09:43:570
25692996058,1cyclictest22044-21kworker/u4:212:20:571
25685996058,1cyclictest27287-21kworker/u4:008:43:570
25685996058,1cyclictest26307-21kworker/u4:012:21:570
25685996058,1cyclictest25136-21kworker/u4:107:24:570
25685996058,1cyclictest1660-21kworker/u4:010:20:580
25685996057,2cyclictest8940-21kworker/u4:011:25:580
25685996057,2cyclictest13993-21kworker/u4:109:19:580
25685996056,2cyclictest13993-21kworker/u4:109:15:580
25685996055,4cyclictest28803-21ssh10:17:570
19222600,1sleep10-21swapper/111:48:531
25685995956,2cyclictest27711-21kworker/u4:311:09:560
25685995955,3cyclictest12063-21diskmemload09:56:550
25685995955,2cyclictest29874-21kworker/u4:109:40:580
25685995955,2cyclictest14514-21kworker/u4:108:13:570
25685995856,1cyclictest25064-21kworker/u4:208:31:580
25685995855,2cyclictest8940-21kworker/u4:011:50:580
25685995855,2cyclictest8940-21kworker/u4:011:20:560
25685995854,3cyclictest0-21swapper/009:09:580
25685995853,4cyclictest17711-21ssh10:43:560
25685995853,4cyclictest12063-21diskmemload10:38:580
25685995853,4cyclictest0-21swapper/009:49:560
25692995755,1cyclictest6655-21kworker/u4:111:57:581
25692995755,1cyclictest1660-21kworker/u4:009:45:571
25685995755,1cyclictest7844-21kworker/u4:107:50:570
25685995755,1cyclictest6655-21kworker/u4:112:13:570
25685995755,1cyclictest30504-21kworker/u4:112:41:570
25685995755,1cyclictest23269-21kworker/u4:111:44:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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