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2023-02-06 - 19:22

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot7.osadl.org (updated Mon Feb 06, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84692900,1sleep00-21swapper/011:16:540
269252860,0sleep00-21swapper/012:16:460
312182740,0sleep10-21swapper/111:05:241
277982680,0sleep10-21swapper/109:41:591
21033996761,5cyclictest0-21swapper/108:40:211
21033996662,3cyclictest0-21swapper/108:05:191
21033996660,4cyclictest0-21swapper/112:21:181
21033996659,6cyclictest0-21swapper/109:18:191
21033996651,14cyclictest0-21swapper/112:04:191
2103399663,61cyclictest1788-21runrttasks09:58:201
2103399663,61cyclictest1788-21runrttasks08:45:181
21033996560,4cyclictest0-21swapper/110:59:201
21033996560,4cyclictest0-21swapper/108:59:201
21033996560,4cyclictest0-21swapper/108:53:201
21033996560,4cyclictest0-21swapper/108:12:191
21033996559,5cyclictest0-21swapper/111:55:181
21033996559,4cyclictest0-21swapper/109:25:181
21033996533,31cyclictest0-21swapper/107:56:191
2103399653,61cyclictest0-21swapper/108:27:191
2103399653,61cyclictest0-21swapper/107:57:201
2103399653,60cyclictest1353-21NetworkManager07:24:221
21033996523,41cyclictest0-21swapper/111:59:191
21033996523,41cyclictest0-21swapper/107:30:211
21033996523,40cyclictest1248-21ssh11:07:201
21033996512,52cyclictest0-21swapper/112:07:181
2102899654,60cyclictest0-21swapper/011:54:190
2102899653,61cyclictest0-21swapper/010:30:170
2102899653,61cyclictest0-21swapper/010:23:200
2102899653,61cyclictest0-21swapper/008:35:210
2102899653,61cyclictest0-21swapper/008:18:210
2102899653,61cyclictest0-21swapper/008:00:190
2102899653,61cyclictest0-21swapper/007:27:190
2102899653,61cyclictest0-21swapper/007:15:210
2102899653,61cyclictest0-21swapper/007:10:210
21033996460,3cyclictest1630-21snmpd07:39:191
21033996460,3cyclictest136650irq/30-eth012:28:191
21033996460,3cyclictest0-21swapper/111:37:201
21033996460,3cyclictest0-21swapper/111:18:191
21033996460,3cyclictest0-21swapper/110:21:201
21033996460,3cyclictest0-21swapper/110:21:201
21033996460,3cyclictest0-21swapper/110:10:181
21033996460,3cyclictest0-21swapper/110:04:211
21033996460,3cyclictest0-21swapper/109:39:191
21033996460,3cyclictest0-21swapper/109:33:191
21033996460,3cyclictest0-21swapper/109:07:201
21033996460,3cyclictest0-21swapper/108:32:191
21033996460,3cyclictest0-21swapper/107:14:221
21033996459,4cyclictest0-21swapper/111:42:201
21033996459,4cyclictest0-21swapper/111:32:201
21033996459,4cyclictest0-21swapper/109:53:191
21033996459,4cyclictest0-21swapper/109:03:191
21033996459,4cyclictest0-21swapper/108:09:211
21033996459,3cyclictest0-21swapper/111:27:181
21033996458,5cyclictest0-21swapper/112:24:201
21033996458,5cyclictest0-21swapper/110:26:181
21033996458,5cyclictest0-21swapper/110:13:191
21033996457,6cyclictest0-21swapper/111:23:201
21033996442,21cyclictest0-21swapper/107:17:191
2103399644,59cyclictest0-21swapper/109:14:191
21033996432,31cyclictest0-21swapper/110:28:191
2103399643,60cyclictest136650irq/30-eth007:44:191
2103399643,60cyclictest0-21swapper/110:39:191
2103399643,60cyclictest0-21swapper/109:48:201
2103399643,60cyclictest0-21swapper/107:34:191
2103399643,60cyclictest0-21swapper/107:07:201
21033996422,41cyclictest0-21swapper/108:47:191
21033996422,41cyclictest0-21swapper/108:23:181
21033996422,41cyclictest0-21swapper/107:48:201
21033996412,51cyclictest0-21swapper/108:17:211
2102899643,60cyclictest0-21swapper/011:57:170
2102899643,60cyclictest0-21swapper/011:43:190
2102899643,60cyclictest0-21swapper/010:59:180
2102899643,60cyclictest0-21swapper/010:51:190
2102899643,60cyclictest0-21swapper/008:49:200
2102899643,60cyclictest0-21swapper/008:45:180
2102899643,60cyclictest0-21swapper/008:38:190
2102899643,60cyclictest0-21swapper/008:29:200
2102899643,60cyclictest0-21swapper/007:54:200
2102899643,60cyclictest0-21swapper/007:49:190
2102899643,60cyclictest0-21swapper/007:42:220
2102899643,60cyclictest0-21swapper/007:38:210
2102899643,60cyclictest0-21swapper/007:26:200
2102899642,61cyclictest0-21swapper/010:44:200
2102899642,61cyclictest0-21swapper/008:15:210
21028996413,50cyclictest0-21swapper/011:34:180
21028996413,50cyclictest0-21swapper/009:02:210
21028996412,51cyclictest0-21swapper/012:11:170
21033996359,3cyclictest0-21swapper/112:35:191
21033996359,3cyclictest0-21swapper/112:12:171
21033996359,3cyclictest0-21swapper/110:47:171
21033996359,3cyclictest0-21swapper/110:43:181
21033996359,3cyclictest0-21swapper/109:28:181
21033996358,4cyclictest0-21swapper/111:12:201
21033996358,4cyclictest0-21swapper/110:54:191
21033996312,50cyclictest4148-21ssh11:49:191
21028996361,1cyclictest28345-21kworker/u4:207:34:180
21028996359,2cyclictest1514-21diskmemload10:02:180
21028996351,11cyclictest0-21swapper/010:53:210
21028996322,40cyclictest2836-21ssh09:52:180
21028996322,40cyclictest0-21swapper/008:09:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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