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2023-03-27 - 15:44

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot7.osadl.org (updated Mon Mar 27, 2023 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129102830,0sleep10-21swapper/111:45:391
257892670,0sleep00-21swapper/010:05:360
208412670,1sleep10-21swapper/110:36:451
22639996657,8cyclictest0-21swapper/110:21:081
22639996657,8cyclictest0-21swapper/109:19:071
22639996657,8cyclictest0-21swapper/107:22:071
22639996556,8cyclictest0-21swapper/108:29:071
22639996523,40cyclictest1353-21NetworkManager12:21:081
22638996561,3cyclictest0-21swapper/010:36:050
2263899653,61cyclictest0-21swapper/012:29:080
2263899653,61cyclictest0-21swapper/008:02:080
2263899653,61cyclictest0-21swapper/007:27:100
2263899653,60cyclictest3255-21diskmemload09:46:090
2263999643,60cyclictest0-21swapper/111:19:081
22638996432,30cyclictest3255-21diskmemload09:10:080
22638996413,50cyclictest5894-21ssh10:20:080
22639996355,7cyclictest12080-21kworker/u4:110:34:051
2263999633,59cyclictest0-21swapper/112:02:061
22639996321,41cyclictest0-21swapper/109:13:061
22638996361,1cyclictest977-21kworker/u4:311:26:080
22638996361,1cyclictest6775-21kworker/u4:211:55:060
22638996361,1cyclictest2308-21kworker/u4:011:39:060
22638996361,1cyclictest20365-21kworker/u4:112:04:080
22639996259,2cyclictest12080-21kworker/u4:110:30:091
22638996260,1cyclictest28014-21kworker/u4:207:21:100
22638996260,1cyclictest16766-21kworker/u4:107:13:070
22638996258,3cyclictest5596-21ssh10:57:070
22638996258,3cyclictest3255-21diskmemload09:54:080
22638996258,3cyclictest0-21swapper/009:30:090
22638996231,30cyclictest0-21swapper/011:01:060
22639996159,1cyclictest0-21swapper/111:06:061
22639996159,1cyclictest0-21swapper/108:48:091
22639996158,2cyclictest0-21swapper/111:12:081
22639996158,2cyclictest0-21swapper/109:42:061
22639996158,2cyclictest0-21swapper/109:09:061
22638996157,3cyclictest0-21swapper/009:58:090
22638996156,4cyclictest0-21swapper/010:53:090
22638996156,4cyclictest0-21swapper/010:25:080
22639996058,1cyclictest0-21swapper/111:33:071
22639996057,2cyclictest0-21swapper/109:38:061
22639996057,2cyclictest0-21swapper/109:38:061
22639996057,2cyclictest0-21swapper/108:24:061
22639996057,2cyclictest0-21swapper/107:58:081
22639996057,2cyclictest0-21swapper/107:06:081
22638996057,2cyclictest16766-21kworker/u4:107:06:100
22638996056,3cyclictest0-21swapper/011:07:050
22638996056,3cyclictest0-21swapper/010:50:060
22638996056,3cyclictest0-21swapper/008:54:340
22639995957,1cyclictest0-21swapper/112:11:081
22639995957,1cyclictest0-21swapper/112:07:071
22639995957,1cyclictest0-21swapper/111:57:081
22639995957,1cyclictest0-21swapper/111:04:071
22639995957,1cyclictest0-21swapper/110:49:061
22639995957,1cyclictest0-21swapper/110:18:081
22639995957,1cyclictest0-21swapper/108:57:061
22639995957,1cyclictest0-21swapper/108:41:071
22639995957,1cyclictest0-21swapper/108:05:081
22639995957,1cyclictest0-21swapper/107:49:081
22639995957,1cyclictest0-21swapper/107:30:091
22639995956,2cyclictest0-21swapper/109:23:081
22639995956,2cyclictest0-21swapper/107:38:071
22639995949,9cyclictest0-21swapper/111:53:061
22638995955,3cyclictest0-21swapper/012:14:060
22638995955,3cyclictest0-21swapper/011:23:070
22638995955,3cyclictest0-21swapper/010:11:070
22639995856,1cyclictest0-21swapper/108:14:081
22639995856,1cyclictest0-21swapper/108:10:081
22639995856,1cyclictest0-21swapper/107:05:091
22639995855,2cyclictest0-21swapper/108:36:091
22639995855,2cyclictest0-21swapper/107:42:101
22639995854,2cyclictest3255-21diskmemload12:28:061
22639995848,9cyclictest0-21swapper/110:08:081
22638995856,1cyclictest24426-21kworker/u4:110:07:070
22638995856,1cyclictest12080-21kworker/u4:110:31:070
22638995854,3cyclictest32483-21ssh09:35:060
22638995854,3cyclictest0-21swapper/012:00:050
22638995854,3cyclictest0-21swapper/011:47:070
22639995755,1cyclictest24426-21kworker/u4:110:15:081
22639995755,1cyclictest17577-21kworker/u4:209:59:071
22639995754,2cyclictest31961-21kworker/u4:109:35:091
22639995748,8cyclictest0-21swapper/107:20:091
22639995747,9cyclictest0-21swapper/111:23:061
22638995755,1cyclictest977-21kworker/u4:311:20:060
22638995755,1cyclictest2993-21kworker/u4:207:53:080
22638995755,1cyclictest2993-21kworker/u4:207:44:090
22638995755,1cyclictest28014-21kworker/u4:207:20:070
22639995654,1cyclictest31289-21kworker/u4:212:16:051
22639995654,1cyclictest22068-21kworker/u4:008:51:081
22639995654,1cyclictest17577-21kworker/u4:209:27:081
22639995654,1cyclictest13002-21kworker/u4:008:17:061
22638995654,1cyclictest6642-21kworker/u4:009:21:070
22638995654,1cyclictest6642-21kworker/u4:009:20:090
22638995654,1cyclictest31359-21kworker/u4:108:47:090
22638995654,1cyclictest2993-21kworker/u4:207:56:090
22638995654,1cyclictest2993-21kworker/u4:207:48:090
22638995654,1cyclictest2993-21kworker/u4:207:36:070
22638995654,1cyclictest24052-21kworker/u4:108:33:090
22638995654,1cyclictest22068-21kworker/u4:008:42:090
22638995654,1cyclictest22068-21kworker/u4:008:40:070
22638995654,1cyclictest22068-21kworker/u4:008:28:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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