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2022-06-30 - 21:45

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack6slot7.osadl.org (updated Thu Jun 30, 2022 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22342820,1sleep119-21rcuc/109:56:091
250212740,6sleep010-21rcuc/007:36:080
161112720,0sleep10-21swapper/109:33:101
15270996361,1cyclictest26692-21kworker/u4:010:31:241
15270996361,1cyclictest21213-21kworker/u4:007:33:251
15270996361,1cyclictest18770-21kworker/u4:011:57:231
15270996361,1cyclictest18770-21kworker/u4:011:49:231
15270996361,1cyclictest18732-21kworker/u4:209:07:221
15270996351,11cyclictest0-21swapper/109:11:241
15266996361,1cyclictest9337-21kworker/u4:210:00:250
15266996361,1cyclictest31769-21kworker/u4:208:29:240
15266996361,1cyclictest31769-21kworker/u4:208:18:250
15266996361,1cyclictest31769-21kworker/u4:208:14:230
15266996361,1cyclictest18732-21kworker/u4:209:11:240
15270996260,1cyclictest31769-21kworker/u4:208:25:241
15270996260,1cyclictest18996-21kworker/u4:107:23:231
15270996260,1cyclictest18732-21kworker/u4:209:05:231
15270996260,1cyclictest18732-21kworker/u4:208:56:241
15270996260,1cyclictest0-21swapper/109:24:251
15270996260,1cyclictest0-21swapper/108:18:251
15270996251,10cyclictest0-21swapper/108:29:241
15270996250,11cyclictest0-21swapper/108:34:241
15270996241,20cyclictest0-21swapper/108:14:231
15266996260,1cyclictest4962-21kworker/u4:109:24:250
15266996260,1cyclictest26147-21ssh11:49:230
15266996260,1cyclictest20951-21kworker/u4:108:47:240
15266996260,1cyclictest16556-21kworker/u4:008:34:240
15266996259,2cyclictest0-21swapper/011:57:230
15266996259,2cyclictest0-21swapper/009:07:220
134732620,1sleep10-21swapper/112:13:441
239112610,0sleep1201ktimersoftd/107:35:591
15270996160,1cyclictest16865-21kworker/u4:307:30:231
15270996159,1cyclictest9337-21kworker/u4:209:48:241
15270996159,1cyclictest28783-21kworker/u4:012:39:261
15270996159,1cyclictest27949-21kworker/u4:109:51:241
15270996150,10cyclictest0-21swapper/108:47:241
15266996159,1cyclictest0-21swapper/010:31:240
15266996158,2cyclictest0-21swapper/008:56:240
15266996158,2cyclictest0-21swapper/007:33:250
15266996158,2cyclictest0-21swapper/007:23:230
15270996058,1cyclictest7868-21ssh10:04:231
15270996058,1cyclictest18961-21kworker/u4:210:19:221
15270996058,1cyclictest18732-21kworker/u4:208:44:231
15270996058,1cyclictest18350-21kworker/u4:011:00:231
15270996058,1cyclictest14410-21kworker/u4:211:39:241
15266996058,1cyclictest4424-21kworker/u4:110:04:230
15266996058,1cyclictest0-21swapper/009:05:230
15266996058,1cyclictest0-21swapper/008:25:240
15266996058,1cyclictest0-21swapper/007:30:230
2525225954,3sleep10-21swapper/112:28:241
15270995957,1cyclictest9337-21kworker/u4:209:30:241
15270995957,1cyclictest1308-21kworker/u4:111:41:241
15270995957,1cyclictest1308-21kworker/u4:111:33:261
15266995957,1cyclictest0-21swapper/012:39:260
15266995957,1cyclictest0-21swapper/009:51:240
15266995957,1cyclictest0-21swapper/009:48:240
15266995955,3cyclictest0-21swapper/011:41:240
15266995955,2cyclictest1551-21diskmemload09:30:240
15270995856,1cyclictest4424-21kworker/u4:110:07:241
15270995856,1cyclictest32284-21kworker/u4:312:43:251
15270995856,1cyclictest3126-21kworker/u4:010:50:231
15270995856,1cyclictest16556-21kworker/u4:008:37:241
15270995856,1cyclictest0-21swapper/110:37:251
15270995855,2cyclictest18770-21kworker/u4:011:51:231
15266995856,1cyclictest9337-21kworker/u4:210:10:240
15266995856,1cyclictest4424-21kworker/u4:110:37:250
15266995856,1cyclictest19701-21ssh10:19:220
15266995856,1cyclictest0-21swapper/011:39:240
15266995856,1cyclictest0-21swapper/011:00:230
15266995856,1cyclictest0-21swapper/008:44:230
15266995855,2cyclictest0-21swapper/011:33:260
15270995755,1cyclictest711-21kworker/u4:212:02:241
15270995755,1cyclictest4424-21kworker/u4:110:25:231
15270995755,1cyclictest4424-21kworker/u4:110:12:251
15270995755,1cyclictest31769-21kworker/u4:208:02:241
15270995755,1cyclictest18350-21kworker/u4:011:03:261
15270995755,1cyclictest18347-21kworker/u4:012:21:261
15270995755,1cyclictest1475-21ssh11:17:251
15270995755,1cyclictest0-21swapper/111:12:261
15270995755,1cyclictest0-21swapper/109:16:221
15270995754,2cyclictest21213-21kworker/u4:007:46:261
15270995754,2cyclictest0-21swapper/109:38:231
15266995755,1cyclictest9337-21kworker/u4:209:38:230
15266995755,1cyclictest4424-21kworker/u4:110:22:230
15266995755,1cyclictest3126-21kworker/u4:010:43:260
15266995755,1cyclictest22686-21kworker/u4:211:12:260
15266995755,1cyclictest18732-21kworker/u4:209:16:220
15266995755,1cyclictest18732-21kworker/u4:208:51:250
15266995755,1cyclictest18350-21kworker/u4:011:17:250
15266995755,1cyclictest14256-21kworker/u4:212:27:230
15266995754,2cyclictest31769-21kworker/u4:208:05:240
15266995754,2cyclictest0-21swapper/010:14:220
15270995654,1cyclictest5543-21kworker/u4:211:24:241
15270995654,1cyclictest14256-21kworker/u4:212:31:251
15270995654,1cyclictest0-21swapper/110:43:261
15270995654,1cyclictest0-21swapper/108:51:251
15270995653,2cyclictest1308-21kworker/u4:111:28:231
15270995653,2cyclictest0-21swapper/109:43:241
15266995654,1cyclictest23798-21kworker/u4:009:43:240
15266995654,1cyclictest21213-21kworker/u4:007:49:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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