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2022-12-02 - 00:32

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot7.osadl.org (updated Wed Nov 30, 2022 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2683621520,6sleep11610399cyclictest10:46:151
275762810,0sleep10-21swapper/110:06:471
26832810,0sleep10-21swapper/110:15:391
205062740,1sleep00-21swapper/010:39:390
271612680,0sleep10-21swapper/111:28:051
1609299663,61cyclictest1308-21dbus-daemon10:18:200
1609299654,60cyclictest0-21swapper/010:04:170
1609299654,60cyclictest0-21swapper/008:48:180
1609299653,61cyclictest0-21swapper/012:06:170
1609299653,61cyclictest0-21swapper/010:23:180
1609299653,61cyclictest0-21swapper/009:23:180
1609299653,61cyclictest0-21swapper/009:17:200
1609299653,61cyclictest0-21swapper/008:24:180
1609299653,61cyclictest0-21swapper/008:18:170
1609299653,61cyclictest0-21swapper/008:03:170
1609299653,61cyclictest0-21swapper/007:08:200
1610399641,62cyclictest0-21swapper/107:38:181
1610399641,62cyclictest0-21swapper/107:23:201
1609299644,59cyclictest0-21swapper/007:22:190
1609299643,60cyclictest4602-21ssh08:56:180
1609299643,60cyclictest0-21swapper/012:19:170
1609299643,60cyclictest0-21swapper/012:02:160
1609299643,60cyclictest0-21swapper/011:16:200
1609299643,60cyclictest0-21swapper/010:46:180
1609299643,60cyclictest0-21swapper/010:10:200
1609299643,60cyclictest0-21swapper/009:50:200
1609299643,60cyclictest0-21swapper/009:31:170
1609299643,60cyclictest0-21swapper/009:05:200
1609299642,61cyclictest0-21swapper/011:50:160
1609299642,61cyclictest0-21swapper/008:54:190
16103996361,1cyclictest18247-21kworker/u4:109:24:201
1610399631,61cyclictest0-21swapper/108:11:181
16092996361,1cyclictest30290-21kworker/u4:311:32:180
16092996361,1cyclictest2975-21kworker/u4:107:43:170
1609299632,60cyclictest0-21swapper/007:37:180
1609299632,60cyclictest0-21swapper/007:01:190
16103996259,2cyclictest30290-21kworker/u4:311:34:161
16092996260,1cyclictest6653-21kworker/u4:207:51:190
16092996241,20cyclictest0-21swapper/011:36:180
16103996159,1cyclictest8960-21kworker/u4:009:15:201
16092996158,2cyclictest0-21swapper/012:21:180
16103996058,1cyclictest18247-21kworker/u4:109:31:201
16103995957,1cyclictest12474-21kworker/u4:309:58:171
16103995854,3cyclictest29398-21kworker/u4:110:23:181
16092995856,1cyclictest7001-21kworker/u4:010:32:180
16092995856,1cyclictest32663-21kworker/u4:209:35:170
16092995856,1cyclictest28216-21kworker/u4:010:51:170
16092995856,1cyclictest19852-21kworker/u4:208:30:190
16092995856,1cyclictest13206-21kworker/u4:208:06:180
16092995856,1cyclictest12474-21kworker/u4:309:57:170
16092995856,1cyclictest0-21swapper/011:24:170
16092995855,2cyclictest6653-21kworker/u4:207:49:180
156952580,0sleep00-21swapper/009:10:380
16103995755,1cyclictest329-21kworker/u4:111:04:161
16103995755,1cyclictest28192-21kworker/u4:008:48:181
16103995754,2cyclictest16655-21kworker/u4:110:04:181
16092995755,1cyclictest8731-21kworker/u4:109:45:170
16092995755,1cyclictest4614-21kworker/u4:209:02:200
16092995755,1cyclictest4512-21kworker/u4:009:40:200
16092995755,1cyclictest20150-21kworker/u4:207:10:200
16092995755,1cyclictest19852-21kworker/u4:208:37:170
1609299573,52cyclictest2373-21diskmemload11:27:190
16103995654,1cyclictest8960-21kworker/u4:009:05:201
16103995654,1cyclictest7868-21kworker/u4:111:50:161
16103995654,1cyclictest28192-21kworker/u4:008:56:181
16103995654,1cyclictest28192-21kworker/u4:008:54:191
16103995654,1cyclictest25563-21kworker/u4:312:06:171
16103995654,1cyclictest22235-21kworker/u4:012:02:161
16103995654,1cyclictest19852-21kworker/u4:208:24:181
16103995654,1cyclictest1731-21kworker/u4:212:19:171
16103995654,1cyclictest11000-21kworker/u4:108:03:171
16103995653,2cyclictest26248-21kworker/u4:107:27:181
16103995653,2cyclictest19852-21kworker/u4:208:33:171
16103995634,21cyclictest0-21swapper/108:05:201
16103995624,31cyclictest0-21swapper/108:17:201
1610399561,54cyclictest0-21swapper/111:06:191
1610399561,54cyclictest0-21swapper/107:44:201
1610399561,54cyclictest0-21swapper/107:11:201
16092995654,1cyclictest6653-21kworker/u4:207:55:210
16092995654,1cyclictest6509-21kworker/u4:011:06:180
16092995654,1cyclictest329-21kworker/u4:111:01:170
16103995554,1cyclictest7582-21kworker/u4:107:08:201
16103995553,1cyclictest20821-21kworker/u4:010:10:201
16103995553,1cyclictest17932-21kworker/u4:007:01:191
16103995553,1cyclictest15145-21kworker/u4:111:16:201
16103995553,1cyclictest12474-21kworker/u4:309:50:191
16103995553,1cyclictest11425-21kworker/u4:210:38:191
1610399551,53cyclictest0-21swapper/111:58:191
1610399551,53cyclictest0-21swapper/111:35:171
1610399551,53cyclictest0-21swapper/111:22:191
1610399551,53cyclictest0-21swapper/110:30:201
1610399551,53cyclictest0-21swapper/108:42:191
1610399551,53cyclictest0-21swapper/108:35:201
1610399551,53cyclictest0-21swapper/107:56:211
1610399551,53cyclictest0-21swapper/107:51:211
1610399551,53cyclictest0-21swapper/107:31:191
1610399541,52cyclictest0-21swapper/106:56:191
16092995433,20cyclictest0-21swapper/010:27:180
1609299542,51cyclictest0-21swapper/010:08:200
1609299542,51cyclictest0-21swapper/007:27:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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