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2022-08-19 - 13:01

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot7.osadl.org (updated Fri Aug 19, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2483421140,0sleep024833-21munin-node20:41:170
313652900,1sleep00-21swapper/019:41:150
1569099773,72cyclictest30665-21ssh00:21:151
1569099732,32cyclictest0-21swapper/121:09:151
1568199693,65cyclictest0-21swapper/020:34:140
1569099673,62cyclictest18358-21expr23:26:131
1568199673,62cyclictest0-21swapper/021:22:150
15681996660,5cyclictest0-21swapper/020:15:160
15681996660,4cyclictest6970-21munin-node22:31:150
15681996660,4cyclictest32644-21ssh23:43:140
1568199663,61cyclictest1742-21runrttasks21:10:140
15690996557,6cyclictest14786-21grep22:01:151
15681996561,3cyclictest0-21swapper/021:20:140
15681996560,4cyclictest15675-21cyclictest20:19:140
15681996560,4cyclictest0-21swapper/023:15:130
15681996560,4cyclictest0-21swapper/022:56:160
15681996560,4cyclictest0-21swapper/022:08:150
15681996560,4cyclictest0-21swapper/019:26:140
15681996560,4cyclictest0-21swapper/019:12:170
15681996559,5cyclictest0-21swapper/022:16:170
15681996559,5cyclictest0-21swapper/000:33:160
15681996559,5cyclictest0-21swapper/000:10:140
1568199655,59cyclictest0-21swapper/000:17:140
1568199654,60cyclictest0-21swapper/020:38:150
15681996533,31cyclictest0-21swapper/020:01:140
1568199653,61cyclictest24000-21ssh00:12:140
1568199653,61cyclictest19032-21ssh23:26:160
1568199653,61cyclictest0-21swapper/023:38:160
1568199653,61cyclictest0-21swapper/020:23:160
1568199653,61cyclictest0-21swapper/019:33:160
1568199653,61cyclictest0-21swapper/019:17:150
1568199652,62cyclictest0-21swapper/023:01:160
15690996455,8cyclictest24640-21kworker/u4:223:34:151
15681996460,3cyclictest391-21ssh21:43:150
15681996460,3cyclictest17144-21ssh22:44:140
15681996460,3cyclictest0-21swapper/023:59:150
15681996460,3cyclictest0-21swapper/023:47:150
15681996460,3cyclictest0-21swapper/023:21:150
15681996460,3cyclictest0-21swapper/023:07:150
15681996460,3cyclictest0-21swapper/022:37:150
15681996460,3cyclictest0-21swapper/022:26:150
15681996460,3cyclictest0-21swapper/022:21:140
15681996460,3cyclictest0-21swapper/022:12:150
15681996460,3cyclictest0-21swapper/022:05:160
15681996460,3cyclictest0-21swapper/021:50:150
15681996460,3cyclictest0-21swapper/021:36:160
15681996460,3cyclictest0-21swapper/021:33:150
15681996460,3cyclictest0-21swapper/019:24:170
15681996460,3cyclictest0-21swapper/019:06:160
15681996459,4cyclictest0-21swapper/023:16:160
15681996459,4cyclictest0-21swapper/021:28:150
15681996459,4cyclictest0-21swapper/021:14:140
15681996459,4cyclictest0-21swapper/020:26:140
15681996459,4cyclictest0-21swapper/019:38:170
15681996459,4cyclictest0-21swapper/000:26:150
15681996459,4cyclictest0-21swapper/000:22:130
1568199644,59cyclictest0-21swapper/020:08:160
1568199643,60cyclictest0-21swapper/020:50:140
15681996413,49cyclictest10169-21munin-node21:56:170
15690996360,2cyclictest30331-21kworker/u4:219:48:171
15690996358,4cyclictest0-21swapper/100:11:141
15690996354,8cyclictest17755-21kworker/u4:221:27:131
15681996359,3cyclictest18603-21ssh22:46:140
15681996359,3cyclictest0-21swapper/023:52:130
15681996359,3cyclictest0-21swapper/023:31:140
15681996359,3cyclictest0-21swapper/022:51:140
15681996359,3cyclictest0-21swapper/020:56:140
15681996359,3cyclictest0-21swapper/020:52:150
15681996359,3cyclictest0-21swapper/020:00:160
15681996359,3cyclictest0-21swapper/019:54:140
15681996359,3cyclictest0-21swapper/019:46:140
15681996359,3cyclictest0-21swapper/000:01:160
1568199632,60cyclictest0-21swapper/021:04:160
15690996260,1cyclictest24748-21kworker/u4:023:01:151
15690996259,2cyclictest20463-21kworker/u4:100:26:131
15690996255,5cyclictest2738-21gltestperf23:06:161
15690996254,7cyclictest416-21kworker/u4:121:50:141
15690996254,7cyclictest15023-21kworker/u4:122:47:151
15690996254,7cyclictest1177-21kworker/u4:123:50:141
15690996253,8cyclictest30331-21kworker/u4:219:57:161
15681996258,3cyclictest0-21swapper/021:53:140
15690996159,1cyclictest12990-21kworker/u4:020:17:171
15690996159,1cyclictest10922-21kworker/u4:123:21:151
15690996157,3cyclictest0-21swapper/122:35:141
15690996155,4cyclictest22939-21sed22:51:151
15690996151,9cyclictest0-21swapper/100:20:131
15690996058,1cyclictest29117-21kworker/u4:023:41:141
15690996057,2cyclictest28339-21kworker/u4:021:43:161
15690995957,1cyclictest12990-21kworker/u4:020:27:171
15690995950,8cyclictest0-21swapper/119:42:171
15690995950,8cyclictest0-21swapper/119:16:161
15690995856,1cyclictest9612-21kworker/u4:022:38:141
15690995856,1cyclictest28339-21kworker/u4:022:08:141
15690995856,1cyclictest1936-21kworker/u4:019:23:171
15690995856,1cyclictest15468-21kworker/u4:119:06:141
15690995855,2cyclictest5598-21kworker/u4:223:54:141
15690995855,2cyclictest17755-21kworker/u4:221:33:141
15690995855,2cyclictest13258-21kworker/u4:121:24:141
15690995853,4cyclictest10693-21fschecks_time21:56:141
15690995850,7cyclictest0-21swapper/100:35:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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