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2023-03-26 - 04:50

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack6slot7.osadl.org (updated Sun Mar 26, 2023 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13452996956,12cyclictest0-21swapper/022:30:530
13452996857,10cyclictest1630-21snmpd23:46:510
58202670,0sleep10-21swapper/121:14:101
1345399674,61cyclictest1353-21NetworkManager21:07:551
238622660,0sleep00-21swapper/022:13:390
1345399663,62cyclictest0-21swapper/121:54:521
13452996662,3cyclictest1343-21dbus-daemon21:42:550
13452996657,8cyclictest0-21swapper/023:52:510
13452996655,10cyclictest30205-21kworker/u4:119:54:520
13453996560,4cyclictest0-21swapper/121:49:521
1345399654,60cyclictest0-21swapper/122:34:541
1345399653,61cyclictest0-21swapper/123:39:521
1345399653,61cyclictest0-21swapper/121:03:531
1345399653,61cyclictest0-21swapper/120:02:531
1345399653,61cyclictest0-21swapper/119:07:531
13452996555,9cyclictest30205-21kworker/u4:119:45:520
13452996554,10cyclictest26551-21kworker/u4:000:23:500
13452996554,10cyclictest25361-21kworker/u4:023:40:510
13452996554,10cyclictest24592-21kworker/u4:020:57:510
13452996554,10cyclictest10478-21kworker/u4:021:23:540
13452996550,13cyclictest26342-21diskmemload00:27:520
1345299653,60cyclictest30670-21ssh23:38:530
13452996513,50cyclictest26342-21diskmemload22:25:520
1345399643,60cyclictest0-21swapper/120:47:531
1345399643,60cyclictest0-21swapper/120:40:531
1345399643,60cyclictest0-21swapper/120:11:521
1345399643,60cyclictest0-21swapper/119:52:551
1345399643,60cyclictest0-21swapper/119:39:551
13452996460,2cyclictest5781-21kworker/u4:223:15:520
13452996455,8cyclictest7536-21kworker/u4:019:00:520
13452996454,9cyclictest3548-21kworker/u4:122:42:510
13452996454,9cyclictest30455-21kworker/u4:121:50:510
13452996454,9cyclictest22464-21kworker/u4:121:30:510
13452996454,9cyclictest1833-21kworker/u4:220:46:520
13452996454,9cyclictest14929-21kworker/u4:119:11:520
13452996454,9cyclictest11651-21kworker/u4:021:59:520
13452996432,31cyclictest0-21swapper/022:17:540
13453996360,2cyclictest16394-21kworker/u4:100:02:531
13453996341,20cyclictest18676-21sh22:06:521
13453996322,40cyclictest0-21swapper/122:19:541
13453996322,40cyclictest0-21swapper/100:27:511
13452996354,8cyclictest7162-21kworker/u4:222:04:510
13452996354,8cyclictest22464-21kworker/u4:121:04:510
13452996354,8cyclictest1833-21kworker/u4:220:30:510
13452996353,9cyclictest20900-21kworker/u4:223:26:510
13452996353,9cyclictest1833-21kworker/u4:220:21:520
13452996341,21cyclictest0-21swapper/020:12:550
13452996331,31cyclictest0-21swapper/021:26:520
13452996312,50cyclictest0-21swapper/022:05:520
13452996312,50cyclictest0-21swapper/019:15:540
13452996260,1cyclictest0-21swapper/020:09:540
13452996259,2cyclictest5781-21kworker/u4:223:10:540
13452996259,2cyclictest25730-21kworker/u4:221:37:540
13452996259,2cyclictest0-21swapper/019:24:550
13452996258,2cyclictest17496-21ssh23:22:510
13452996250,11cyclictest0-21swapper/019:06:550
13452996250,11cyclictest0-21swapper/000:10:510
13453996155,5cyclictest0-21swapper/100:13:521
13452996157,3cyclictest0-21swapper/020:40:530
13452996157,3cyclictest0-21swapper/000:07:510
13452996157,2cyclictest31304-21ssh22:21:530
13452996157,2cyclictest15129-21ssh23:58:520
13453996058,1cyclictest3548-21kworker/u4:122:38:521
13453996058,1cyclictest2497-21kworker/u4:123:46:531
13453996057,2cyclictest20356-21kworker/u4:122:20:511
13453996055,4cyclictest0-21swapper/100:17:521
13453996055,4cyclictest0-21swapper/100:17:521
13452996058,1cyclictest0-21swapper/021:14:540
13452996057,2cyclictest16394-21kworker/u4:100:04:540
13452996057,2cyclictest0-21swapper/023:05:530
13452996056,3cyclictest0-21swapper/021:16:540
13452996056,2cyclictest24276-21kworker/u4:322:57:530
13453995956,2cyclictest22464-21kworker/u4:121:15:541
13453995956,2cyclictest12781-21kworker/u4:022:56:511
13453995955,3cyclictest0-21swapper/120:20:521
13453995954,4cyclictest0-21swapper/123:23:531
13453995954,4cyclictest0-21swapper/122:52:511
13452995957,1cyclictest24276-21kworker/u4:322:52:540
13452995957,1cyclictest0-21swapper/000:16:510
13452995957,1cyclictest0-21swapper/000:16:510
13452995956,2cyclictest10235-21kworker/u4:123:30:540
13453995854,3cyclictest0-21swapper/122:01:511
13453995854,3cyclictest0-21swapper/121:44:541
13453995854,3cyclictest0-21swapper/119:34:521
13452995855,2cyclictest30455-21kworker/u4:121:47:550
13452995849,8cyclictest0-21swapper/021:05:520
13453995755,1cyclictest25361-21kworker/u4:023:33:531
13453995755,1cyclictest22464-21kworker/u4:121:28:521
13453995755,1cyclictest1833-21kworker/u4:220:37:541
13453995755,1cyclictest10478-21kworker/u4:021:23:531
13452995755,1cyclictest9157-21kworker/u4:120:16:540
13452995755,1cyclictest30205-21kworker/u4:119:55:550
13452995755,1cyclictest22464-21kworker/u4:120:52:510
13452995748,8cyclictest21182-21ssh22:48:510
13453995654,1cyclictest30205-21kworker/u4:119:55:551
13453995654,1cyclictest21460-21kworker/u4:021:32:531
13453995654,1cyclictest1833-21kworker/u4:220:29:541
13453995654,1cyclictest1833-21kworker/u4:220:09:531
13453995652,3cyclictest0-21swapper/123:44:531
13453995651,4cyclictest0-21swapper/122:27:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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