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2019-07-16 - 03:19

Pentium(R) Dual-Core CPU T4500 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot7.osadl.org (updated Mon Jul 15, 2019 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70952770,1sleep00-21swapper/023:47:410
154252760,0sleep00-21swapper/023:14:580
3189099713,67cyclictest0-21swapper/100:16:011
30742700,0sleep00-21swapper/022:59:470
31890996952,4cyclictest0-21swapper/121:32:011
31890996927,41cyclictest31878-21cyclictest23:17:011
31890996854,3cyclictest0-21swapper/122:27:591
31890996853,3cyclictest0-21swapper/100:10:031
3188099685,62cyclictest0-21swapper/023:58:010
3188099685,62cyclictest0-21swapper/021:29:020
3188099684,63cyclictest0-21swapper/020:38:000
31890996761,4cyclictest1244-21NetworkManager00:04:031
31890996754,3cyclictest0-21swapper/122:16:011
3188099674,62cyclictest0-21swapper/021:59:000
3188099674,62cyclictest0-21swapper/000:22:000
83272660,0sleep10-21swapper/122:23:081
31890996660,4cyclictest1234-21dbus-daemon21:44:031
31890996655,9cyclictest5629-21ssh23:02:021
31890996655,1cyclictest18343-21kworker/u4:020:14:591
31890996654,3cyclictest0-21swapper/120:39:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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