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2023-12-10 - 15:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot7.osadl.org (updated Sun Dec 10, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89292830,1sleep00-21swapper/010:09:000
3098996761,5cyclictest0-21swapper/111:38:511
3098996760,5cyclictest16937-21ssh12:18:491
309899673,62cyclictest21761-21diskmemload09:25:511
3098996661,4cyclictest0-21swapper/112:03:491
3098996661,4cyclictest0-21swapper/110:18:511
3098996660,5cyclictest0-21swapper/108:32:501
309899664,60cyclictest1289-21NetworkManager12:08:521
309899664,60cyclictest1289-21NetworkManager07:54:521
309899664,60cyclictest1279-21dbus-daemon10:32:521
309899664,60cyclictest1279-21dbus-daemon09:20:521
309899663,61cyclictest0-21swapper/111:56:511
3097996661,4cyclictest0-21swapper/012:01:500
3097996660,4cyclictest1706-21runrttasks07:58:520
3097996623,41cyclictest2959-21kworker/0:009:29:510
3098996561,3cyclictest0-21swapper/111:30:491
3098996561,3cyclictest0-21swapper/111:02:511
3098996561,3cyclictest0-21swapper/110:54:501
3098996561,3cyclictest0-21swapper/110:48:491
3098996561,3cyclictest0-21swapper/110:22:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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