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2022-05-28 - 13:47

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot7.osadl.org (updated Sat May 28, 2022 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
138921170,5sleep1982099cyclictest20:09:491
85292800,7sleep0981299cyclictest22:39:330
221052800,1sleep18-21rcu_preempt21:42:281
9820996760,6cyclictest32016-21kworker/u4:000:21:231
9062640,0sleep00-21swapper/021:54:540
9820996361,1cyclictest6724-21kworker/u4:223:13:231
9820996361,1cyclictest32699-21kworker/u4:220:15:261
9820996361,1cyclictest0-21swapper/120:29:251
9820996360,2cyclictest0-21swapper/100:42:261
9812996361,1cyclictest9059-21kworker/u4:122:12:240
9812996361,1cyclictest7076-21kworker/u4:020:29:250
9812996361,1cyclictest19842-21kworker/u4:221:08:240
9812996361,1cyclictest19608-21kworker/u4:200:42:260
9812996360,2cyclictest0-21swapper/023:13:230
9820996260,1cyclictest12425-21kworker/u4:122:55:241
9820996260,1cyclictest12425-21kworker/u4:122:52:251
9820996260,1cyclictest0-21swapper/121:08:241
9812996259,2cyclictest4774-21ssh00:21:230
9812996251,10cyclictest0-21swapper/020:15:260
9820996159,1cyclictest15679-21kworker/u4:200:04:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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