You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-02-06 - 14:51

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot7.osadl.org (updated Mon Feb 06, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84692900,1sleep00-21swapper/011:16:540
269252860,0sleep00-21swapper/012:16:460
312182740,0sleep10-21swapper/111:05:241
277982680,0sleep10-21swapper/109:41:591
21033996761,5cyclictest0-21swapper/108:40:211
21033996662,3cyclictest0-21swapper/108:05:191
21033996660,4cyclictest0-21swapper/112:21:181
21033996659,6cyclictest0-21swapper/109:18:191
21033996651,14cyclictest0-21swapper/112:04:191
2103399663,61cyclictest1788-21runrttasks09:58:201
2103399663,61cyclictest1788-21runrttasks08:45:181
21033996560,4cyclictest0-21swapper/110:59:201
21033996560,4cyclictest0-21swapper/108:59:201
21033996560,4cyclictest0-21swapper/108:53:201
21033996560,4cyclictest0-21swapper/108:12:191
21033996559,5cyclictest0-21swapper/111:55:181
21033996559,4cyclictest0-21swapper/109:25:181
21033996533,31cyclictest0-21swapper/107:56:191
2103399653,61cyclictest0-21swapper/108:27:191
2103399653,61cyclictest0-21swapper/107:57:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional