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2021-06-16 - 23:08

Pentium(R) Dual-Core CPU T4500 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot7.osadl.org (updated Wed Jun 16, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180212730,0sleep00-21swapper/011:42:390
171872720,2sleep00-21swapper/010:14:570
1307599683,62cyclictest12575-21rm11:34:540
216292670,1sleep10-21swapper/110:21:411
1307599675,60cyclictest22759-21ssh11:05:540
1307599673,63cyclictest27463-21ssh11:12:520
1307599664,61cyclictest0-21swapper/007:24:520
13081996561,3cyclictest0-21swapper/111:26:541
13081996560,4cyclictest0-21swapper/110:13:531
1308199653,61cyclictest0-21swapper/107:55:541
1307599653,61cyclictest0-21swapper/010:58:540
1307599653,61cyclictest0-21swapper/009:41:530
13081996460,3cyclictest0-21swapper/110:46:531
13081996460,3cyclictest0-21swapper/109:05:521
13081996460,3cyclictest0-21swapper/108:09:521
13081996460,3cyclictest0-21swapper/107:15:531
13081996459,4cyclictest0-21swapper/108:52:531
13081996459,4cyclictest0-21swapper/108:28:521
13081996459,4cyclictest0-21swapper/108:17:521
13081996458,5cyclictest0-21swapper/110:37:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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