You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-01-30 - 06:23

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Mon Jan 30, 2023 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1760121220,0sleep117603-21fschecks_time23:17:431
113532860,1sleep00-21swapper/022:32:420
278142790,0sleep00-21swapper/022:52:120
2269099663,62cyclictest0-21swapper/121:19:091
2269099663,62cyclictest0-21swapper/119:52:111
108772660,0sleep10-21swapper/123:47:431
52692650,0sleep00-21swapper/021:47:290
2269099653,61cyclictest0-21swapper/120:12:111
2269099653,61cyclictest0-21swapper/119:37:091
2269099653,61cyclictest0-21swapper/119:13:111
2269099652,62cyclictest0-21swapper/121:02:091
22690996461,2cyclictest8826-21kworker/u4:123:53:091
22690996459,4cyclictest0-21swapper/119:41:111
2269099644,59cyclictest0-21swapper/100:23:101
2269099643,60cyclictest0-21swapper/121:06:101
2269099643,60cyclictest0-21swapper/120:19:081
2269099643,60cyclictest0-21swapper/120:07:111
2269099643,60cyclictest0-21swapper/119:25:111
2269099642,61cyclictest0-21swapper/123:36:091
2269099642,61cyclictest0-21swapper/120:33:091
22682996461,2cyclictest14673-21kworker/u4:120:46:100
22682996460,3cyclictest18397-21kworker/u4:219:25:110
22690996360,2cyclictest0-21swapper/122:26:081
22690996360,2cyclictest0-21swapper/122:11:111
22690996352,10cyclictest0-21swapper/123:00:091
2269099632,60cyclictest0-21swapper/121:49:101
22682996361,1cyclictest31917-21kworker/u4:023:36:090
22682996361,1cyclictest18397-21kworker/u4:219:52:110
22682996361,1cyclictest18397-21kworker/u4:219:37:090
22682996361,1cyclictest14673-21kworker/u4:120:12:110
22682996360,2cyclictest32383-21kworker/u4:222:28:090
22682996360,2cyclictest14673-21kworker/u4:121:02:080
104852630,0sleep00-21swapper/023:08:380
22690996260,1cyclictest0-21swapper/121:10:091
22690996260,1cyclictest0-21swapper/119:59:081
22690996260,1cyclictest0-21swapper/119:09:111
22690996259,2cyclictest0-21swapper/121:43:081
22690996259,2cyclictest0-21swapper/121:28:101
22690996259,2cyclictest0-21swapper/120:29:101
22690996259,2cyclictest0-21swapper/120:26:101
22690996259,2cyclictest0-21swapper/119:57:091
22690996259,2cyclictest0-21swapper/100:31:081
22682996260,1cyclictest6320-21kworker/u4:221:19:090
22682996260,1cyclictest6320-21kworker/u4:221:11:090
22682996260,1cyclictest28912-21kworker/u4:200:23:100
22682996260,1cyclictest18397-21kworker/u4:219:20:100
22682996260,1cyclictest18397-21kworker/u4:219:13:110
22682996260,1cyclictest18152-21kworker/u4:000:03:080
22682996260,1cyclictest14673-21kworker/u4:121:06:100
22682996260,1cyclictest14673-21kworker/u4:120:33:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional