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2022-06-27 - 17:21

x86 Intel Pentium Dual-Core T4500 @2300 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Mon Jun 27, 2022 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57932780,2sleep00-21swapper/008:35:540
317092720,1sleep031715-21needreboot09:26:020
392399703,66cyclictest0-21swapper/111:52:211
3923996858,9cyclictest0-21swapper/112:34:221
391599685,62cyclictest0-21swapper/011:45:240
3923996759,7cyclictest0-21swapper/108:31:241
3923996758,8cyclictest0-21swapper/112:06:221
3923996758,8cyclictest0-21swapper/108:22:221
3915996761,5cyclictest9012-21ssh10:19:240
391599675,61cyclictest0-21swapper/011:32:230
3923996660,4cyclictest1749-21runrttasks08:07:231
3923996658,7cyclictest0-21swapper/111:57:231
3923996658,7cyclictest0-21swapper/109:49:231
3923996658,7cyclictest0-21swapper/107:23:221
3923996657,8cyclictest0-21swapper/110:14:221
392399663,62cyclictest6738-21ssh11:36:251
3915996661,4cyclictest0-21swapper/010:40:220
391599665,60cyclictest0-21swapper/009:50:240
391599663,62cyclictest0-21swapper/010:01:230
391599663,62cyclictest0-21swapper/009:19:230
391599663,62cyclictest0-21swapper/007:45:230
3923996556,8cyclictest8500-21kworker/u4:109:40:211
3923996533,31cyclictest0-21swapper/109:05:241
3923996533,30cyclictest1305-21dbus-daemon10:04:251
392399653,61cyclictest0-21swapper/110:52:231
392399653,61cyclictest0-21swapper/110:37:221
392399653,61cyclictest0-21swapper/110:21:231
392399653,61cyclictest0-21swapper/107:19:221
3923996514,50cyclictest0-21swapper/109:53:231
3915996561,3cyclictest0-21swapper/012:16:210
3915996561,3cyclictest0-21swapper/010:54:230
3915996561,3cyclictest0-21swapper/010:08:240
3915996561,3cyclictest0-21swapper/007:56:240
3915996560,4cyclictest0-21swapper/012:27:220
3915996560,4cyclictest0-21swapper/012:02:230
3915996560,4cyclictest0-21swapper/011:57:240
3915996560,4cyclictest0-21swapper/011:48:210
3915996560,4cyclictest0-21swapper/010:29:230
3915996560,4cyclictest0-21swapper/009:41:220
3915996560,4cyclictest0-21swapper/008:01:220
3915996559,5cyclictest0-21swapper/009:24:220
391599654,60cyclictest0-21swapper/012:21:210
391599652,62cyclictest0-21swapper/012:44:240
3923996460,3cyclictest0-21swapper/111:23:221
3923996459,4cyclictest0-21swapper/112:23:221
3923996459,4cyclictest0-21swapper/111:15:211
3923996459,4cyclictest0-21swapper/108:17:221
3923996459,4cyclictest0-21swapper/107:38:211
3923996457,6cyclictest0-21swapper/111:33:251
3923996455,8cyclictest8146-21kworker/u4:211:41:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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