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2024-10-04 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Thu Oct 03, 2024 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7317:24:314547
80,17:24:384546
"maxima":[4545
017:23:184542
0,17:23:184541
0,17:23:184540
0,17:23:184539
0,17:23:184538
0,17:23:184537
0,17:23:184536
0,17:23:184535
0,17:23:184534
0,17:23:184533
0,17:23:184532
0,17:23:184531
0,17:23:184530
0,17:23:184529
0,17:23:184528
0,17:23:184527
0,17:23:184526
0,17:23:184525
0,17:23:184524
0,17:23:184523
0,17:23:184522
0,17:23:184521
0,17:23:184520
0,17:23:184519
0,17:23:184518
0,17:23:184517
0,17:23:184516
0,17:23:184515
0,17:23:184514
0,17:23:184513
0,17:23:184512
0,17:23:184511
0,17:23:184510
0,17:23:184509
0,17:23:184508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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