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2022-01-26 - 12:51

Pentium(R) Dual-Core CPU T4500 @ 2.30GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #6, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Wed Jan 26, 2022 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61342750,1sleep10-21swapper/122:47:461
596999675,61cyclictest0-21swapper/021:23:040
596999675,61cyclictest0-21swapper/021:12:050
596999675,61cyclictest0-21swapper/020:22:030
596999674,62cyclictest0-21swapper/022:44:020
596999674,62cyclictest0-21swapper/022:07:050
596999674,62cyclictest0-21swapper/022:07:050
596999674,62cyclictest0-21swapper/022:00:040
596999674,62cyclictest0-21swapper/020:44:050
596999674,62cyclictest0-21swapper/019:43:040
596999674,62cyclictest0-21swapper/000:27:050
596999674,62cyclictest0-21swapper/000:21:020
596999674,61cyclictest0-21swapper/019:19:020
596999673,63cyclictest0-21swapper/023:23:020
596999673,63cyclictest0-21swapper/021:41:040
596999673,63cyclictest0-21swapper/020:49:040
596999673,63cyclictest0-21swapper/020:38:040
596999673,63cyclictest0-21swapper/019:58:020
5969996662,3cyclictest0-21swapper/023:54:050
5969996662,3cyclictest0-21swapper/019:26:050
5969996661,4cyclictest0-21swapper/023:38:050
5969996661,4cyclictest0-21swapper/020:58:050
596999665,60cyclictest0-21swapper/021:16:020
596999664,61cyclictest0-21swapper/023:26:050
596999664,61cyclictest0-21swapper/023:18:050
596999664,61cyclictest0-21swapper/023:13:020
596999664,61cyclictest0-21swapper/021:48:040
596999664,61cyclictest0-21swapper/021:37:020
596999664,61cyclictest0-21swapper/021:31:040
596999664,61cyclictest0-21swapper/020:51:040
596999664,61cyclictest0-21swapper/020:27:030
596999664,61cyclictest0-21swapper/020:14:050
596999664,61cyclictest0-21swapper/019:11:050
596999664,61cyclictest0-21swapper/000:16:040
596999664,61cyclictest0-21swapper/000:06:040
596999663,62cyclictest0-21swapper/023:49:030
596999663,62cyclictest0-21swapper/023:42:030
596999663,62cyclictest0-21swapper/023:31:050
596999663,62cyclictest0-21swapper/023:08:040
596999663,62cyclictest0-21swapper/023:01:050
596999663,62cyclictest0-21swapper/022:58:030
596999663,62cyclictest0-21swapper/022:51:050
596999663,62cyclictest0-21swapper/022:32:050
596999663,62cyclictest0-21swapper/022:26:030
596999663,62cyclictest0-21swapper/022:18:020
596999663,62cyclictest0-21swapper/022:11:050
596999663,62cyclictest0-21swapper/022:01:030
596999663,62cyclictest0-21swapper/021:26:040
596999663,62cyclictest0-21swapper/021:06:050
596999663,62cyclictest0-21swapper/021:04:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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