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2024-07-21 - 06:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Thu Jul 18, 2024 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7317:36:054547
80,17:36:124546
"maxima":[4545
017:34:524542
0,17:34:524541
0,17:34:524540
0,17:34:524539
0,17:34:524538
0,17:34:524537
0,17:34:524536
0,17:34:524535
0,17:34:524534
0,17:34:524533
0,17:34:524532
0,17:34:524531
0,17:34:524530
0,17:34:524529
0,17:34:524528
0,17:34:524527
0,17:34:524526
0,17:34:524525
0,17:34:524524
0,17:34:524523
0,17:34:524522
0,17:34:524521
0,17:34:524520
0,17:34:524519
0,17:34:524518
0,17:34:524517
0,17:34:524516
0,17:34:524515
0,17:34:524514
0,17:34:524513
0,17:34:524512
0,17:34:524511
0,17:34:524510
0,17:34:524509
0,17:34:524508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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