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2024-11-04 - 09:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Nov 04, 2024 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3245999707699,7cyclictest4927-21kerneloops21:39:203
3245999707699,7cyclictest4927-21kerneloops21:39:203
3244699707700,6cyclictest4927-21kerneloops21:56:071
3244099707698,7cyclictest4927-21kerneloops19:15:450
3244099707698,7cyclictest4927-21kerneloops00:26:380
3244699706699,5cyclictest4927-21kerneloops23:57:081
3244099706698,6cyclictest4927-21kerneloops19:58:530
3245999705701,2cyclictest4927-21kerneloops22:20:413
3245999705699,5cyclictest4927-21kerneloops21:18:203
3245999705697,6cyclictest4927-21kerneloops21:11:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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