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2026-05-19 - 12:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue May 19, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2355699637628,7cyclictest4793-21kerneloops00:27:363
2355699637628,7cyclictest4793-21kerneloops00:27:353
2355699635628,6cyclictest4793-21kerneloops21:25:553
2355699635627,6cyclictest4793-21kerneloops23:31:563
2354099635628,5cyclictest4793-21kerneloops23:12:281
2355699634627,6cyclictest4793-21kerneloops23:56:253
2355699634627,6cyclictest4793-21kerneloops19:33:393
2355699634627,6cyclictest4793-21kerneloops19:10:313
2355699634626,6cyclictest4793-21kerneloops19:18:253
2354099634627,5cyclictest4793-21kerneloops00:08:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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