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2024-02-24 - 04:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 24, 2024 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479811340,1123rtkit-daemon4927-21kerneloops19:08:123
899499588578,8cyclictest4927-21kerneloops22:12:500
901399586578,6cyclictest4927-21kerneloops23:52:453
901399585579,4cyclictest4927-21kerneloops23:41:043
900799585576,7cyclictest4927-21kerneloops21:40:372
899499585577,7cyclictest4927-21kerneloops23:13:130
901399584578,4cyclictest4927-21kerneloops23:01:563
901399584576,6cyclictest4927-21kerneloops00:26:493
899999584577,6cyclictest4927-21kerneloops22:18:071
899999584575,7cyclictest4927-21kerneloops22:32:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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