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2024-06-25 - 08:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Jun 25, 2024 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2934799624620,2cyclictest4927-21kerneloops23:06:362
2935299612604,6cyclictest4927-21kerneloops19:37:123
2934099611603,6cyclictest4927-21kerneloops23:26:021
2934099611603,6cyclictest4927-21kerneloops23:19:551
2935299610603,5cyclictest4927-21kerneloops23:27:053
2934099610602,7cyclictest4927-21kerneloops23:50:521
2934099610602,6cyclictest4927-21kerneloops22:43:271
2934099610602,6cyclictest4927-21kerneloops20:25:411
2934099610601,7cyclictest4927-21kerneloops23:45:271
2934099610601,7cyclictest4927-21kerneloops23:45:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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