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2024-04-26 - 00:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 25, 2024 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312199616612,2cyclictest4927-21kerneloops10:45:390
312199615603,10cyclictest4927-21kerneloops09:23:470
314399612607,3cyclictest4927-21kerneloops11:43:233
314399612607,3cyclictest4927-21kerneloops11:43:233
312699612605,5cyclictest4927-21kerneloops12:07:111
314399610603,6cyclictest4927-21kerneloops11:11:003
313799610600,8cyclictest4927-21kerneloops11:12:162
312699610603,5cyclictest4927-21kerneloops11:08:211
312699610602,6cyclictest4927-21kerneloops08:27:161
312699610601,7cyclictest4927-21kerneloops12:00:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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