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2025-07-15 - 22:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Jul 15, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2712199710701,7cyclictest4927-21kerneloops12:22:413
2712199709702,5cyclictest4927-21kerneloops11:18:593
2712199709701,7cyclictest4927-21kerneloops11:47:223
2710999709703,4cyclictest4927-21kerneloops07:43:411
2710999709699,8cyclictest4927-21kerneloops07:15:201
2711799707698,7cyclictest4927-21kerneloops11:59:082
2710599707700,5cyclictest4927-21kerneloops08:21:420
2712199706702,2cyclictest4927-21kerneloops09:55:133
2710999706701,4cyclictest4927-21kerneloops09:09:491
2710999706699,5cyclictest4927-21kerneloops09:46:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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