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2025-06-18 - 23:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Jun 18, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482199722713,7cyclictest4927-21kerneloops09:50:582
2480699713709,2cyclictest4927-21kerneloops11:06:180
2481499712704,6cyclictest4927-21kerneloops11:53:431
2481499710702,6cyclictest4927-21kerneloops08:46:371
2480699710701,7cyclictest4927-21kerneloops08:23:530
2481499709702,5cyclictest4927-21kerneloops10:25:521
2481499709702,5cyclictest4927-21kerneloops10:25:511
2480699709698,9cyclictest4927-21kerneloops12:10:350
2482799708702,4cyclictest4927-21kerneloops07:53:083
2482799708701,6cyclictest4927-21kerneloops12:26:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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