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2023-09-26 - 15:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Sep 26, 2023 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143039910401031,7cyclictest6576-21kerneloops10:23:193
143039910381029,7cyclictest6576-21kerneloops10:12:013
143019910371026,9cyclictest6576-21kerneloops09:37:492
143009910331024,7cyclictest6576-21kerneloops08:10:321
143009910311022,7cyclictest6576-21kerneloops08:00:321
143039910301023,5cyclictest6576-21kerneloops09:00:513
143039910301022,6cyclictest6576-21kerneloops07:19:483
143039910291022,5cyclictest6576-21kerneloops10:50:523
143039910291022,5cyclictest6576-21kerneloops10:50:513
143039910291022,5cyclictest6576-21kerneloops09:21:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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