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2025-04-21 - 11:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 21, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
384899720716,2cyclictest4927-21kerneloops23:05:412
384399710701,7cyclictest4927-21kerneloops23:54:311
384899709700,7cyclictest4927-21kerneloops19:39:492
384399709702,6cyclictest4927-21kerneloops21:26:291
385399708702,5cyclictest4927-21kerneloops23:54:103
384399708701,5cyclictest4927-21kerneloops20:26:041
383699708699,7cyclictest4927-21kerneloops00:25:580
385399707702,4cyclictest4927-21kerneloops22:47:003
385399707701,4cyclictest4927-21kerneloops23:23:143
385399707700,5cyclictest4927-21kerneloops19:44:533
385399707699,6cyclictest4927-21kerneloops21:12:113
384899707699,6cyclictest4927-21kerneloops21:23:002
384399707701,5cyclictest4927-21kerneloops22:01:091
384399707699,7cyclictest4927-21kerneloops23:10:251
385399706698,6cyclictest4927-21kerneloops21:28:353
384899706698,6cyclictest4927-21kerneloops21:02:032
384899706697,7cyclictest4927-21kerneloops20:51:052
385399705699,4cyclictest4927-21kerneloops00:21:583
385399705697,7cyclictest4927-21kerneloops21:16:573
384899705698,5cyclictest4927-21kerneloops22:57:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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