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2024-07-27 - 03:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jul 27, 2024 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479810970,1087rtkit-daemon4927-21kerneloops19:08:261
2824099658649,7cyclictest4927-21kerneloops19:14:351
2823699658646,8cyclictest4927-21kerneloops19:51:320
2825199657649,6cyclictest4927-21kerneloops22:39:212
2825799656650,5cyclictest4927-21kerneloops22:28:413
2825799656650,5cyclictest4927-21kerneloops22:04:033
2824099656651,4cyclictest4927-21kerneloops00:01:321
2825799655649,5cyclictest4927-21kerneloops21:59:373
2825799655649,5cyclictest4927-21kerneloops21:59:363
2825799655648,6cyclictest4927-21kerneloops20:11:303
2825799655647,6cyclictest4927-21kerneloops22:14:083
2825199655647,6cyclictest4927-21kerneloops22:26:552
2825199655647,6cyclictest4927-21kerneloops19:26:462
2824099655649,4cyclictest4927-21kerneloops22:25:401
2823699655646,7cyclictest4927-21kerneloops21:53:010
2825799654652,1cyclictest4927-21kerneloops23:45:343
2825799654649,4cyclictest4927-21kerneloops19:44:203
2824099654649,4cyclictest4927-21kerneloops21:11:541
2824099653646,5cyclictest4927-21kerneloops20:01:181
2824099653645,6cyclictest4927-21kerneloops20:51:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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