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2019-07-22 - 08:29

Intel(R) Core(TM) i3-2350M CPU @ 2.30GHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 22, 2019 00:44:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139399593584,7cyclictest6488-21kerneloops19:15:021
139399584577,5cyclictest6488-21kerneloops23:01:441
138899584573,10cyclictest6488-21kerneloops22:13:510
139399583576,5cyclictest6488-21kerneloops22:43:571
139399583576,5cyclictest6488-21kerneloops22:17:051
139399582576,5cyclictest6488-21kerneloops22:36:301
139899581573,6cyclictest6488-21kerneloops21:01:423
139799581573,6cyclictest6488-21kerneloops22:27:172
139799581571,8cyclictest6488-21kerneloops21:55:222
139899580574,5cyclictest6488-21kerneloops19:29:203
139799580574,5cyclictest6488-21kerneloops20:31:262
139799580572,6cyclictest6488-21kerneloops21:13:112
139899579571,6cyclictest6488-21kerneloops19:32:133
139799579573,5cyclictest6488-21kerneloops21:36:412
139799579572,5cyclictest6488-21kerneloops00:26:142
139399579576,2cyclictest6488-21kerneloops20:54:011
138899579569,8cyclictest6488-21kerneloops21:15:110
139899578572,5cyclictest6488-21kerneloops00:00:243
139799578573,4cyclictest6488-21kerneloops19:18:252
139799578572,5cyclictest6488-21kerneloops23:49:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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