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2024-12-09 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Dec 09, 2024 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
614999709701,6cyclictest4927-21kerneloops07:16:003
613799708701,5cyclictest4927-21kerneloops12:33:011
614999706697,7cyclictest4927-21kerneloops11:12:403
613799706699,5cyclictest4927-21kerneloops09:54:001
613799705698,6cyclictest4927-21kerneloops08:03:061
613799705698,5cyclictest4927-21kerneloops11:40:281
614999704700,2cyclictest4927-21kerneloops07:53:183
613299704696,6cyclictest4927-21kerneloops08:16:420
613299704696,6cyclictest4927-21kerneloops08:16:420
613299704696,6cyclictest4927-21kerneloops08:02:140
614999703698,4cyclictest4927-21kerneloops10:25:143
614999703696,5cyclictest4927-21kerneloops09:54:433
614999703695,6cyclictest4927-21kerneloops09:25:573
614399703698,4cyclictest4927-21kerneloops11:02:012
614399703696,6cyclictest4927-21kerneloops07:21:112
613799703699,2cyclictest4927-21kerneloops10:05:561
613799703696,5cyclictest4927-21kerneloops10:53:561
614999702699,2cyclictest4927-21kerneloops09:19:403
614999702696,5cyclictest4927-21kerneloops07:32:353
614399702694,6cyclictest4927-21kerneloops10:10:532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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