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2024-04-16 - 10:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Apr 16, 2024 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1676299613603,8cyclictest4927-21kerneloops23:44:481
1676299612603,7cyclictest4927-21kerneloops19:25:511
1677799611604,6cyclictest4927-21kerneloops22:36:323
1677799610603,6cyclictest4927-21kerneloops00:01:533
1676299610604,5cyclictest4927-21kerneloops22:49:501
1676299610603,6cyclictest4927-21kerneloops22:34:021
1676299609603,5cyclictest4927-21kerneloops22:52:421
1676299609603,4cyclictest4927-21kerneloops21:28:311
1677799608604,2cyclictest4927-21kerneloops21:32:243
1676299608603,4cyclictest4927-21kerneloops21:40:471
1675699608600,7cyclictest4927-21kerneloops19:26:130
1677799607599,6cyclictest4927-21kerneloops20:29:543
1676299607600,6cyclictest4927-21kerneloops19:50:571
1677799606600,5cyclictest4927-21kerneloops21:20:293
1677799606598,6cyclictest4927-21kerneloops23:13:483
1676299606603,1cyclictest4927-21kerneloops23:50:151
1676299606599,5cyclictest4927-21kerneloops20:47:541
1675699606600,5cyclictest4927-21kerneloops21:04:150
1675699606599,6cyclictest4927-21kerneloops22:24:010
1675699606598,6cyclictest4927-21kerneloops20:23:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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