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2023-12-11 - 04:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Dec 11, 2023 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80969819050,1893rtkit-daemon6576-21kerneloops19:06:250
319279910601051,7cyclictest6576-21kerneloops21:48:572
319259910481037,9cyclictest6576-21kerneloops21:58:100
319289910331023,8cyclictest6576-21kerneloops21:42:333
319269910331025,6cyclictest6576-21kerneloops22:25:411
319289910321024,6cyclictest6576-21kerneloops00:29:133
319269910311024,5cyclictest6576-21kerneloops23:59:101
319269910311024,5cyclictest6576-21kerneloops23:59:091
319289910301023,5cyclictest6576-21kerneloops19:45:153
319279910301021,7cyclictest6576-21kerneloops23:25:212
319279910301021,7cyclictest6576-21kerneloops00:29:252
319269910301024,5cyclictest6576-21kerneloops00:04:141
319289910291023,5cyclictest6576-21kerneloops19:24:253
319279910291021,6cyclictest6576-21kerneloops23:19:442
319269910291022,5cyclictest6576-21kerneloops19:39:081
319289910281021,5cyclictest6576-21kerneloops21:38:033
319279910281021,5cyclictest6576-21kerneloops22:18:042
319279910281020,6cyclictest6576-21kerneloops21:51:472
319279910281017,9cyclictest6576-21kerneloops23:49:292
319269910281020,6cyclictest6576-21kerneloops23:02:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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