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2025-07-02 - 07:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jul 02, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3214099725722,2cyclictest4927-21kerneloops22:41:273
3214099710704,5cyclictest4927-21kerneloops20:08:073
3214099709704,4cyclictest4927-21kerneloops19:56:243
3214099708701,5cyclictest4927-21kerneloops22:59:193
3212899708701,5cyclictest4927-21kerneloops20:30:071
3212899708700,6cyclictest4927-21kerneloops00:25:241
3212099708700,6cyclictest4927-21kerneloops23:22:150
3213399707700,6cyclictest4927-21kerneloops23:49:142
3213399707700,6cyclictest4927-21kerneloops21:47:042
3212899707703,2cyclictest4927-21kerneloops20:48:021
3212099707700,6cyclictest4927-21kerneloops00:29:200
3212099707699,6cyclictest4927-21kerneloops19:29:560
3214099706700,4cyclictest4927-21kerneloops23:38:023
3214099705703,1cyclictest4927-21kerneloops19:32:473
3214099705697,6cyclictest4927-21kerneloops19:36:413
3213399705696,7cyclictest4927-21kerneloops00:27:312
3213399705695,8cyclictest4927-21kerneloops21:37:462
3212899705699,5cyclictest4927-21kerneloops23:00:131
3212899705698,5cyclictest4927-21kerneloops19:20:391
3212899705696,7cyclictest4927-21kerneloops00:34:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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