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2026-06-11 - 03:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jun 11, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2963999637628,7cyclictest4793-21kerneloops00:05:252
2962999637628,7cyclictest4793-21kerneloops21:18:551
2962999636627,7cyclictest4793-21kerneloops23:04:531
2962499636624,10cyclictest4793-21kerneloops23:15:410
2963999635626,7cyclictest4793-21kerneloops23:10:442
2963999635626,7cyclictest4793-21kerneloops22:53:302
2962999635627,6cyclictest4793-21kerneloops22:39:041
2962499635624,9cyclictest4793-21kerneloops21:40:190
2964599633627,5cyclictest4793-21kerneloops22:23:083
2963999633625,6cyclictest4793-21kerneloops21:48:462
2963999633625,6cyclictest4793-21kerneloops20:04:102
2962999633626,5cyclictest4793-21kerneloops23:49:451
2962499633625,7cyclictest4793-21kerneloops21:30:400
2962499633624,7cyclictest4793-21kerneloops19:51:000
2964599632627,4cyclictest4793-21kerneloops20:49:173
2964599632627,4cyclictest4793-21kerneloops19:56:403
2964599632626,4cyclictest4793-21kerneloops20:09:323
2963999632625,5cyclictest4793-21kerneloops23:30:532
2963999632625,5cyclictest4793-21kerneloops00:10:312
2962499632624,7cyclictest4793-21kerneloops19:44:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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