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2026-02-09 - 16:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Feb 09, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
854299649641,7cyclictest4793-21kerneloops11:39:372
854299644641,2cyclictest4793-21kerneloops11:50:172
853099636632,2cyclictest4793-21kerneloops11:33:170
853099635623,10cyclictest4793-21kerneloops09:14:570
855199634624,8cyclictest4793-21kerneloops12:15:233
853599634626,6cyclictest4793-21kerneloops12:38:471
855199633626,5cyclictest4793-21kerneloops09:35:273
853599633626,5cyclictest4793-21kerneloops11:40:411
853599633626,5cyclictest4793-21kerneloops09:58:551
853599633626,5cyclictest4793-21kerneloops09:58:551
853099633624,7cyclictest4793-21kerneloops11:13:180
855199632625,5cyclictest4793-21kerneloops09:01:373
855199632624,7cyclictest4793-21kerneloops07:51:403
853099632624,6cyclictest4793-21kerneloops11:58:190
853099632624,6cyclictest4793-21kerneloops11:54:580
853099632622,8cyclictest4793-21kerneloops11:40:200
853599631623,6cyclictest4793-21kerneloops08:15:201
853099631624,6cyclictest4793-21kerneloops09:46:440
853099631624,5cyclictest4793-21kerneloops11:46:350
853099631623,6cyclictest4793-21kerneloops09:34:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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