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2023-06-09 - 13:56

x86 Intel Core i3-2350M @2300 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Fri Jun 09, 2023 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195009910441031,11cyclictest6576-21kerneloops00:29:000
195009910311019,10cyclictest6576-21kerneloops23:45:150
195049910301021,7cyclictest6576-21kerneloops22:56:203
195019910281022,5cyclictest6576-21kerneloops23:55:151
195019910281020,6cyclictest6576-21kerneloops21:12:481
195019910281020,6cyclictest6576-21kerneloops20:42:001
195019910281018,8cyclictest6576-21kerneloops21:08:311
195019910271020,6cyclictest6576-21kerneloops00:39:461
195019910271020,5cyclictest6576-21kerneloops23:28:351
195019910271020,5cyclictest6576-21kerneloops22:52:181
195019910271020,5cyclictest6576-21kerneloops21:26:581
195019910271020,5cyclictest6576-21kerneloops20:50:471
195019910271018,7cyclictest6576-21kerneloops22:37:031
195019910271018,7cyclictest6576-21kerneloops00:11:041
195049910261018,6cyclictest6576-21kerneloops22:50:043
195019910261019,5cyclictest6576-21kerneloops23:20:301
195019910261019,5cyclictest6576-21kerneloops21:01:401
195049910251017,7cyclictest6576-21kerneloops22:31:493
195049910251016,7cyclictest6576-21kerneloops19:35:353
195019910251018,5cyclictest6576-21kerneloops23:54:261
195019910251018,5cyclictest6576-21kerneloops23:49:421
195019910251018,5cyclictest6576-21kerneloops22:27:171
195019910251018,5cyclictest6576-21kerneloops21:37:131
195019910251018,5cyclictest6576-21kerneloops21:16:251
195019910251018,5cyclictest6576-21kerneloops20:06:081
195019910251018,5cyclictest6576-21kerneloops19:54:441
195019910251018,5cyclictest6576-21kerneloops19:35:261
195019910251018,5cyclictest6576-21kerneloops00:05:161
195019910251018,5cyclictest6576-21kerneloops00:03:221
195019910251017,6cyclictest6576-21kerneloops23:06:411
195019910251017,6cyclictest6576-21kerneloops21:40:281
195019910251017,6cyclictest6576-21kerneloops20:17:441
195009910251012,11cyclictest6576-21kerneloops23:57:500
195049910241018,5cyclictest6576-21kerneloops23:16:403
195049910241018,5cyclictest6576-21kerneloops23:16:393
195049910241017,5cyclictest6576-21kerneloops21:52:143
195019910241017,5cyclictest6576-21kerneloops20:55:111
195019910241017,5cyclictest6576-21kerneloops20:28:291
195019910241017,5cyclictest6576-21kerneloops19:47:101
195019910241017,5cyclictest6576-21kerneloops19:31:511
195009910241017,6cyclictest6576-21kerneloops19:26:250
195009910241016,6cyclictest6576-21kerneloops20:14:590
195009910241016,6cyclictest6576-21kerneloops20:14:580
195049910231016,5cyclictest6576-21kerneloops22:36:213
195049910231016,5cyclictest6576-21kerneloops00:37:393
195049910231014,7cyclictest6576-21kerneloops20:01:483
195019910231016,5cyclictest6576-21kerneloops20:46:111
195019910231016,5cyclictest6576-21kerneloops19:28:441
195019910231015,6cyclictest6576-21kerneloops20:21:551
195009910231015,6cyclictest6576-21kerneloops00:38:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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