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2024-06-15 - 22:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 15, 2024 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2861299621610,9cyclictest4927-21kerneloops11:54:490
2861299618608,8cyclictest4927-21kerneloops10:08:540
2863499614604,8cyclictest4927-21kerneloops11:26:223
2863499613604,7cyclictest4927-21kerneloops11:22:573
2863499612604,6cyclictest4927-21kerneloops09:11:443
2863499611604,5cyclictest4927-21kerneloops07:34:383
2863499611603,6cyclictest4927-21kerneloops12:23:253
2863499611603,6cyclictest4927-21kerneloops08:24:203
2861799611604,6cyclictest4927-21kerneloops09:25:541
2861799611603,6cyclictest4927-21kerneloops07:15:121
2861799610604,5cyclictest4927-21kerneloops11:12:281
2861799610604,4cyclictest4927-21kerneloops07:56:361
2861799610603,6cyclictest4927-21kerneloops11:50:371
2861799610603,5cyclictest4927-21kerneloops12:38:341
2861799610603,5cyclictest4927-21kerneloops12:14:341
2861799610603,5cyclictest4927-21kerneloops12:14:331
2861799610603,5cyclictest4927-21kerneloops11:56:241
2861799610603,5cyclictest4927-21kerneloops09:58:281
2861799610602,7cyclictest4927-21kerneloops09:41:281
2861799610602,6cyclictest4927-21kerneloops07:47:081
2861299610602,6cyclictest4927-21kerneloops09:43:450
2861799609604,4cyclictest4927-21kerneloops11:00:111
2861799609603,5cyclictest4927-21kerneloops08:03:371
2861799609602,5cyclictest4927-21kerneloops08:09:111
2861799609602,5cyclictest4927-21kerneloops07:30:021
2861799609602,5cyclictest4927-21kerneloops07:26:261
2863499608602,5cyclictest4927-21kerneloops08:05:323
2863499608600,6cyclictest4927-21kerneloops07:56:463
2862899608604,2cyclictest4927-21kerneloops12:02:372
2861799608602,5cyclictest4927-21kerneloops08:38:081
2861799608600,6cyclictest4927-21kerneloops11:24:241
2861799608600,6cyclictest4927-21kerneloops07:23:461
2861299608601,5cyclictest4927-21kerneloops09:01:430
2861299608599,7cyclictest4927-21kerneloops09:10:070
2863499607604,2cyclictest4927-21kerneloops09:39:013
2863499607601,5cyclictest4927-21kerneloops10:08:443
2862899607600,6cyclictest4927-21kerneloops08:05:212
2861799607602,4cyclictest4927-21kerneloops08:11:521
2861799607601,5cyclictest4927-21kerneloops07:38:351
2863499606601,4cyclictest4927-21kerneloops08:36:423
2862899606598,6cyclictest4927-21kerneloops10:07:192
2861799606600,4cyclictest4927-21kerneloops10:12:311
2861299606599,5cyclictest4927-21kerneloops09:29:560
2863499605597,6cyclictest4927-21kerneloops10:35:263
2863499605597,6cyclictest4927-21kerneloops08:58:143
2861799605597,6cyclictest4927-21kerneloops12:28:511
2861799605596,7cyclictest4927-21kerneloops10:43:281
2861299605598,5cyclictest4927-21kerneloops07:18:470
2863499604596,6cyclictest4927-21kerneloops12:10:413
2863499604596,6cyclictest4927-21kerneloops12:10:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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