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2022-06-27 - 17:25

x86 Intel Core i3-2350M @2300 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Mon Jun 27, 2022 12:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24399991006993,11cyclictest6576-21kerneloops09:32:170
24400991001992,7cyclictest6576-21kerneloops10:57:381
2440099997990,5cyclictest6576-21kerneloops08:43:281
2440299996990,5cyclictest6576-21kerneloops12:13:003
2440299996988,6cyclictest6576-21kerneloops11:58:023
2440299996988,6cyclictest6576-21kerneloops11:58:023
2440099996989,5cyclictest6576-21kerneloops11:44:581
2439999996988,6cyclictest6576-21kerneloops09:06:010
2440099995988,5cyclictest6576-21kerneloops08:53:071
2439999995986,7cyclictest6576-21kerneloops07:51:180
2439999995984,9cyclictest6576-21kerneloops09:25:140
2439999995981,12cyclictest6576-21kerneloops10:25:500
2440199994987,5cyclictest6576-21kerneloops09:31:462
2440199994986,6cyclictest6576-21kerneloops09:43:272
2440199994985,7cyclictest6576-21kerneloops09:35:442
2440099994985,8cyclictest6576-21kerneloops10:53:291
2440099994985,7cyclictest6576-21kerneloops09:16:581
2440099994985,7cyclictest6576-21kerneloops07:37:091
2439999994985,7cyclictest6576-21kerneloops11:36:110
2439999994984,8cyclictest6576-21kerneloops08:43:190
2440299993985,6cyclictest6576-21kerneloops09:00:563
2440299993985,6cyclictest6576-21kerneloops08:34:373
2440199993986,5cyclictest6576-21kerneloops11:20:082
2440199993983,8cyclictest6576-21kerneloops08:51:542
2440099993988,4cyclictest6576-21kerneloops10:39:311
2440099993986,5cyclictest6576-21kerneloops08:36:141
2440099993984,7cyclictest6576-21kerneloops09:06:321
2440099993983,8cyclictest6576-21kerneloops11:51:031
2439999993985,6cyclictest6576-21kerneloops08:13:350
2439999993984,7cyclictest6576-21kerneloops08:22:150
2440299992984,6cyclictest6576-21kerneloops08:25:043
2440199992986,5cyclictest6576-21kerneloops09:02:182
2440199992985,5cyclictest6576-21kerneloops11:08:152
2440199992982,8cyclictest6576-21kerneloops11:13:492
2440099992984,6cyclictest6576-21kerneloops07:45:431
2440099992983,7cyclictest6576-21kerneloops11:29:261
2440099992982,8cyclictest6576-21kerneloops10:45:301
2439999992984,6cyclictest6576-21kerneloops07:48:570
2439999992982,8cyclictest6576-21kerneloops11:53:280
2440299991984,5cyclictest6576-21kerneloops09:47:103
2440299991983,6cyclictest6576-21kerneloops07:26:183
2440099991985,5cyclictest6576-21kerneloops11:48:271
2440099991985,5cyclictest6576-21kerneloops09:57:101
2440099991984,5cyclictest6576-21kerneloops11:12:031
2440099991984,5cyclictest6576-21kerneloops10:14:561
2440299990983,5cyclictest6576-21kerneloops10:22:133
2440299990983,5cyclictest6576-21kerneloops10:22:123
2440299990982,6cyclictest6576-21kerneloops10:39:413
2440199990983,6cyclictest6576-21kerneloops09:45:472
2440199990983,5cyclictest6576-21kerneloops07:57:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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