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2026-05-15 - 04:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Fri May 15, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
515899635628,5cyclictest4793-21kerneloops00:06:231
515899635626,7cyclictest4793-21kerneloops21:51:171
515199635626,7cyclictest4793-21kerneloops21:22:170
516399634626,6cyclictest4793-21kerneloops19:36:022
516399634625,7cyclictest4793-21kerneloops00:17:502
515199634624,8cyclictest4793-21kerneloops19:50:010
515199634624,8cyclictest4793-21kerneloops19:50:010
515199633620,11cyclictest4793-21kerneloops22:23:320
517199632626,5cyclictest4793-21kerneloops20:49:033
515899632625,5cyclictest4793-21kerneloops22:54:201
517199631628,2cyclictest4793-21kerneloops23:50:023
516399631625,5cyclictest4793-21kerneloops20:24:192
515199631622,7cyclictest4793-21kerneloops23:33:070
517199630626,2cyclictest4793-21kerneloops21:35:453
517199630626,2cyclictest4793-21kerneloops21:35:453
517199630622,6cyclictest4793-21kerneloops22:27:103
516399630624,5cyclictest4793-21kerneloops23:36:512
516399630624,5cyclictest4793-21kerneloops21:34:402
516399630624,5cyclictest4793-21kerneloops20:47:582
516399630624,5cyclictest4793-21kerneloops19:43:272
516399630623,5cyclictest4793-21kerneloops20:18:582
515899630624,5cyclictest4793-21kerneloops19:47:341
515899630623,5cyclictest4793-21kerneloops00:23:481
517199629627,1cyclictest4793-21kerneloops23:47:143
517199629627,1cyclictest4793-21kerneloops22:16:273
517199629626,2cyclictest4793-21kerneloops22:54:313
517199629620,7cyclictest4793-21kerneloops21:21:033
516399629622,5cyclictest4793-21kerneloops23:15:402
515899629626,2cyclictest4793-21kerneloops19:29:411
515899629622,6cyclictest4793-21kerneloops21:40:311
515199629622,5cyclictest4793-21kerneloops23:48:500
515199629620,7cyclictest4793-21kerneloops00:31:050
516399628625,2cyclictest4793-21kerneloops20:58:292
516399628621,5cyclictest4793-21kerneloops19:17:462
515899628626,1cyclictest4793-21kerneloops20:05:341
515899628624,2cyclictest4793-21kerneloops20:16:581
515199628621,6cyclictest4793-21kerneloops21:11:520
516399627622,4cyclictest4793-21kerneloops19:53:052
516399627622,4cyclictest4793-21kerneloops19:53:052
515899627623,2cyclictest4793-21kerneloops21:46:221
515199627619,6cyclictest4793-21kerneloops19:19:230
517199626624,1cyclictest4793-21kerneloops19:31:593
517199626620,4cyclictest4793-21kerneloops20:10:343
516399626618,6cyclictest4793-21kerneloops21:12:032
515899626623,2cyclictest4793-21kerneloops00:26:071
515899626622,2cyclictest4793-21kerneloops23:29:111
515199626624,1cyclictest4793-21kerneloops22:37:250
515199626619,6cyclictest4793-21kerneloops20:42:080
515199626617,7cyclictest4793-21kerneloops20:54:330
517199625618,5cyclictest4793-21kerneloops19:23:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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