You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-07-14 - 11:34
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 14, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2942199710699,9cyclictest4927-21kerneloops22:03:512
2942899709703,4cyclictest4927-21kerneloops20:46:353
2942899709700,7cyclictest4927-21kerneloops20:26:053
2941699709701,6cyclictest4927-21kerneloops20:47:291
2941699708701,5cyclictest4927-21kerneloops20:01:201
2942899707697,8cyclictest4927-21kerneloops00:03:343
2941699707700,5cyclictest4927-21kerneloops22:32:031
2941699707699,6cyclictest4927-21kerneloops22:50:431
2940799707698,8cyclictest4927-21kerneloops21:18:290
2941699706699,5cyclictest4927-21kerneloops23:11:481
2941699706699,5cyclictest4927-21kerneloops21:08:001
2940799706699,5cyclictest4927-21kerneloops20:35:050
2940799706699,5cyclictest4927-21kerneloops20:35:050
2940799706698,6cyclictest4927-21kerneloops23:09:330
2942899705699,4cyclictest4927-21kerneloops20:43:373
2942899705698,5cyclictest4927-21kerneloops21:18:073
2942899705697,6cyclictest4927-21kerneloops19:19:153
2940799705698,5cyclictest4927-21kerneloops19:29:410
2940799705697,7cyclictest4927-21kerneloops20:10:270
2942199704699,4cyclictest4927-21kerneloops21:12:142
2942199704698,4cyclictest4927-21kerneloops21:38:332
2942199704697,5cyclictest4927-21kerneloops23:31:502
2941699704701,2cyclictest4927-21kerneloops23:30:011
2941699704701,2cyclictest4927-21kerneloops19:57:241
2941699704700,2cyclictest4927-21kerneloops00:39:021
2942899703697,4cyclictest4927-21kerneloops20:33:383
2942899703697,4cyclictest4927-21kerneloops19:24:213
2942899703695,6cyclictest4927-21kerneloops00:30:293
2941699703699,2cyclictest4927-21kerneloops23:23:471
2941699703696,5cyclictest4927-21kerneloops00:25:521
2941699703695,6cyclictest4927-21kerneloops21:38:541
2942899702695,5cyclictest4927-21kerneloops00:24:273
2942199702694,6cyclictest4927-21kerneloops23:52:212
2942199702694,6cyclictest4927-21kerneloops23:52:202
2942199702694,6cyclictest4927-21kerneloops22:25:162
2941699702698,2cyclictest4927-21kerneloops21:32:181
2940799702694,6cyclictest4927-21kerneloops00:16:210
2940799702691,9cyclictest4927-21kerneloops21:00:010
2942899701698,2cyclictest4927-21kerneloops20:18:233
2942199701698,2cyclictest4927-21kerneloops20:22:462
2942199701694,5cyclictest4927-21kerneloops21:25:512
2942199701691,8cyclictest4927-21kerneloops22:08:142
2941699701698,2cyclictest4927-21kerneloops19:35:001
2941699701698,2cyclictest4927-21kerneloops00:04:391
2941699701697,2cyclictest4927-21kerneloops23:44:171
2941699701694,5cyclictest4927-21kerneloops22:49:501
2941699701694,5cyclictest4927-21kerneloops22:08:351
2940799701692,8cyclictest4927-21kerneloops23:15:180
2940799701692,7cyclictest4927-21kerneloops21:58:140
2940799701691,8cyclictest4927-21kerneloops20:42:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional