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2025-11-17 - 06:52

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2s.osadl.org (updated Mon Nov 17, 2025 00:48:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250320699279147,111cyclictest2527440-21kworker/u9:10+rpciod21:40:290
250320699278160,104cyclictest2536370-21ntp_kernel_pll_22:11:100
250320699278147,116cyclictest0-21swapper/023:41:140
250320699273195,49cyclictest171rcu_preempt22:26:360
250320699272141,93cyclictest1-21systemd20:42:280
250320699269134,85cyclictest0-21swapper/019:30:200
250320699267139,92cyclictest2557170-21/usr/sbin/munin23:50:460
250320699266201,53cyclictest0-21swapper/022:40:250
250320699266201,53cyclictest0-21swapper/022:40:240
250320699265153,94cyclictest0-21swapper/021:21:090
250320699263159,87cyclictest0-21swapper/022:37:080
250320699262172,75cyclictest0-21swapper/019:25:320
250320699262172,75cyclictest0-21swapper/019:25:320
250320699262154,49cyclictest171rcu_preempt23:05:520
250320699262154,49cyclictest171rcu_preempt23:05:510
250320699261144,103cyclictest2503205-21cyclictest00:24:510
250320699261144,103cyclictest2503205-21cyclictest00:24:510
250320699260157,86cyclictest0-21swapper/021:18:090
250320699260157,86cyclictest0-21swapper/021:18:090
250320699260148,95cyclictest0-21swapper/021:36:370
250320699259154,89cyclictest0-21swapper/021:50:540
250320699259153,90cyclictest0-21swapper/022:47:080
250320699259153,90cyclictest0-21swapper/022:47:070
250320699259146,98cyclictest2550013-21rm23:16:310
250320699259146,98cyclictest2550013-21rm23:16:310
250320699259143,99cyclictest0-21swapper/020:20:240
250320699259143,99cyclictest0-21swapper/020:20:230
250320699258153,90cyclictest0-21swapper/022:55:040
250320699257152,91cyclictest2526815-21irqstats21:25:500
250320699257152,91cyclictest2526815-21irqstats21:25:490
250320699257150,86cyclictest2546285-21kworker/u10:8-rpciod23:38:330
250320699257150,86cyclictest2546285-21kworker/u10:8-rpciod23:38:320
250320699256152,89cyclictest0-21swapper/000:02:140
250320699256149,98cyclictest0-21swapper/000:31:030
250320699256145,97cyclictest2508826-21grep19:41:580
250320699255138,102cyclictest0-21swapper/021:10:070
250320699254156,84cyclictest0-21swapper/020:45:380
250320699254156,84cyclictest0-21swapper/020:45:380
250320699254145,95cyclictest0-21swapper/000:10:160
250320699254145,95cyclictest0-21swapper/000:10:160
250320699253153,84cyclictest2523479-21ssh21:10:300
250320699252143,92cyclictest0-21swapper/022:35:030
250320699251151,85cyclictest0-21swapper/000:05:550
250320699251151,85cyclictest0-21swapper/000:05:550
250320699251148,87cyclictest9150irq/87-eth%d19:21:070
250320699251146,90cyclictest0-21swapper/020:40:010
250320699251146,90cyclictest0-21swapper/020:40:010
250320699251142,94cyclictest717-21lldpd20:01:280
250320699251139,94cyclictest0-21swapper/023:25:250
250320699249155,78cyclictest0-21swapper/021:46:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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