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2026-01-24 - 06:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Sat Jan 24, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38599654,41cyclictest24953-21ssh23:55:131
402995846,8cyclictest28366irq/58-eth021:45:103
38599492,41cyclictest1594-21ssh22:30:121
37799495,29cyclictest5234-21ssh22:50:120
37799495,29cyclictest5234-21ssh22:50:120
37799492,39cyclictest19460-21ssh00:10:120
38599471,34cyclictest10522-21ssh22:35:111
39499462,24cyclictest31782-21ssh21:35:122
38599442,31cyclictest16010-21ssh23:50:131
39499439,23cyclictest0-21swapper/222:00:132
39499424,28cyclictest6854-21ssh22:15:122
39499424,28cyclictest6854-21ssh22:15:122
385994122,8cyclictest21-21ksoftirqd/121:45:101
37799411,3cyclictest131rcu_preempt23:05:110
40299405,22cyclictest28366irq/58-eth019:20:153
402994021,13cyclictest28366irq/58-eth021:55:133
39499408,13cyclictest12439-21ssh23:30:122
38599403,28cyclictest3169-21ssh21:55:141
38599401,31cyclictest8873-21ssh23:10:131
40299395,21cyclictest28366irq/58-eth022:15:123
40299395,21cyclictest28366irq/58-eth022:15:123
394993919,13cyclictest27-21ksoftirqd/200:30:132
38599375,24cyclictest18498-21diskmemload23:05:111
37799374,7cyclictest131rcu_preempt21:10:130
37799374,7cyclictest131rcu_preempt21:10:130
38599361,26cyclictest73-21kswapd022:20:111
38599353,24cyclictest19475-21ssh00:10:131
37799353,5cyclictest131rcu_preempt19:30:110
377993514,4cyclictest131rcu_preempt21:50:110
40299343,18cyclictest28366irq/58-eth023:25:143
40299342,21cyclictest28366irq/58-eth020:40:123
39499341,23cyclictest17469-21ssh21:45:092
38599343,21cyclictest17728-21ssh23:15:111
37799342,28cyclictest1494-21ssh00:00:140
39499333,18cyclictest27-21ksoftirqd/223:25:132
385993311,13cyclictest19622-21sh22:40:121
37799334,26cyclictest12205-21ssh22:00:120
40299322,19cyclictest28366irq/58-eth022:05:113
40299322,17cyclictest28366irq/58-eth023:05:113
39499322,17cyclictest4997-21ssh00:20:132
377993224,5cyclictest12-21ksoftirqd/019:20:140
40299312,17cyclictest28366irq/58-eth022:55:133
402993115,9cyclictest28366irq/58-eth021:40:143
40299311,20cyclictest28366irq/58-eth023:30:123
40299311,19cyclictest28366irq/58-eth022:20:113
39499312,21cyclictest23261-21ntp_192.168.11422:40:242
38599311,24cyclictest0-21swapper/100:30:121
37799312,27cyclictest21350-21ssh23:35:110
37799312,16cyclictest12-21ksoftirqd/019:50:120
39499301,24cyclictest0-21swapper/221:50:132
38599303,21cyclictest26829-21ssh23:20:131
37799304,23cyclictest14000-21ssh00:25:140
40299296,14cyclictest28366irq/58-eth000:30:133
39499299,12cyclictest27-21ksoftirqd/219:25:132
39499295,13cyclictest22346irq/40-dwc2_hso21:20:132
39499292,20cyclictest5926-21ssh00:37:242
39499292,16cyclictest22346irq/40-dwc2_hso20:30:122
39499291,10cyclictest10537-21ssh22:35:122
385992911,9cyclictest0-21swapper/121:10:121
385992911,9cyclictest0-21swapper/121:10:121
37799293,23cyclictest8429-21sh21:40:140
402992812,11cyclictest28366irq/58-eth000:12:583
39499286,17cyclictest27-21ksoftirqd/223:17:242
39499283,18cyclictest22346irq/40-dwc2_hso00:25:142
39499283,17cyclictest22346irq/40-dwc2_hso22:25:152
394992819,3cyclictest1488-21ssh00:00:142
38599282,21cyclictest10504-21ssh00:05:131
385992814,8cyclictest0-21swapper/123:25:131
37799282,4cyclictest131rcu_preempt00:30:130
37799280,26cyclictest13711-21ssh21:25:120
40299271,15cyclictest28366irq/58-eth023:45:143
39499278,14cyclictest7611-21kworker/2:120:25:132
39499278,14cyclictest7611-21kworker/2:120:25:132
39499275,17cyclictest27-21ksoftirqd/222:14:242
37799272,19cyclictest3252-21ssh00:18:240
37799272,18cyclictest531-21usb-storage20:15:110
37799272,16cyclictest14206-21ssh22:55:120
40299262,16cyclictest28366irq/58-eth000:05:123
40299260,17cyclictest28366irq/58-eth021:10:143
40299260,17cyclictest28366irq/58-eth021:10:143
39499267,13cyclictest27-21ksoftirqd/223:40:352
39499263,10cyclictest27-21ksoftirqd/222:23:512
39499262,10cyclictest0-21swapper/221:40:142
39499261,19cyclictest0-21swapper/221:55:142
39499261,17cyclictest27131-21ls20:45:142
39499261,17cyclictest15692-21ls23:50:022
38599262,18cyclictest13064-21ssh00:24:241
37799265,14cyclictest8869-21ssh23:10:130
40299258,9cyclictest28366irq/58-eth023:15:133
40299255,7cyclictest28366irq/58-eth019:15:133
40299254,14cyclictest0-21swapper/322:25:153
40299253,15cyclictest28466irq/59-eth000:25:143
40299253,11cyclictest28366irq/58-eth020:50:113
39499259,8cyclictest27-21ksoftirqd/221:31:132
39499258,11cyclictest27-21ksoftirqd/223:13:582
39499254,4cyclictest131rcu_preempt00:10:272
39499253,12cyclictest22346irq/40-dwc2_hso20:55:142
39499251,12cyclictest28716-21idleruntime00:15:162
37799251,17cyclictest21290-21ssh22:05:120
40299243,14cyclictest0-21swapper/300:37:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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