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2025-07-15 - 15:04

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot4s.osadl.org (updated Tue Jul 15, 2025 12:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
480999596,37cyclictest22869-21ssh11:20:171
480999567,6cyclictest131rcu_preempt07:20:141
480999567,39cyclictest22248-21ssh11:40:161
480999566,34cyclictest17853-21ssh09:50:121
4827995432,15cyclictest32466irq/58-eth011:05:153
480999521,8cyclictest131rcu_preempt08:50:141
480999521,8cyclictest131rcu_preempt08:50:131
481899502,26cyclictest14043-21ssh12:15:152
481899501,26cyclictest10154-21ssh10:50:142
480199492,41cyclictest17510-21ssh10:55:150
481899481,37cyclictest0-21swapper/208:35:132
4801994725,17cyclictest12-21ksoftirqd/011:50:190
4801994612,23cyclictest12-21ksoftirqd/009:05:140
481899443,30cyclictest19955-21sshd10:35:162
480999434,7cyclictest131rcu_preempt12:05:121
4809994325,6cyclictest21-21ksoftirqd/110:00:151
482799425,28cyclictest32466irq/58-eth010:30:153
482799425,28cyclictest32466irq/58-eth010:30:143
4827993919,14cyclictest32466irq/58-eth009:30:123
480999393,24cyclictest23273-21ssh09:10:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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