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2024-10-10 - 21:21

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Thu Oct 10, 2024 12:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16653996229,25cyclictest22146irq/40-dwc2_hso09:00:102
1663799582,46cyclictest32461-21sendmail-msp08:00:130
16637995735,19cyclictest19390-21sendmail-msp08:20:120
1665399544,39cyclictest20885-21ssh10:05:122
16637995016,25cyclictest12-21ksoftirqd/009:55:110
16637994939,7cyclictest26217-21sendmail-msp07:20:110
1663799492,42cyclictest12-21ksoftirqd/009:10:150
16637994915,9cyclictest131rcu_preempt08:15:140
16637994915,9cyclictest131rcu_preempt08:15:130
1665399481,41cyclictest11277-21sendmail-msp10:20:112
16661994738,6cyclictest0-21swapper/310:20:113
1663799452,35cyclictest3914-21sendmail-msp11:20:120
1666199441,25cyclictest25866irq/58-eth011:45:123
1664599442,34cyclictest11277-21sendmail-msp10:20:121
1664599441,33cyclictest12631-21sendmail-msp10:00:121
1663799445,6cyclictest131rcu_preempt10:50:110
1666199421,26cyclictest25866irq/58-eth010:55:113
1664599411,33cyclictest6334-21sendmail-msp08:40:131
1663799412,35cyclictest25660-21sendmail-msp09:00:110
16661994012,16cyclictest25866irq/58-eth010:10:113
1663799404,6cyclictest12-21ksoftirqd/008:50:120
1665399392,21cyclictest1111-21vmstat11:15:312
1663799394,8cyclictest131rcu_preempt10:55:110
1663799384,17cyclictest12-21ksoftirqd/008:40:130
1663799381,34cyclictest9627-21ssh11:45:130
1663799381,32cyclictest1825-21sendmail-msp11:40:130
1663799373,31cyclictest8122-21ssh09:35:120
1665399362,28cyclictest2511-21ssh12:08:322
16653993615,14cyclictest27-21ksoftirqd/207:15:122
1665399361,18cyclictest25663-21ssh09:25:122
1664599361,24cyclictest15426-21ssh09:40:111
1663799352,25cyclictest9099-21sendmail-msp10:40:120
1665399342,16cyclictest18005-21sendmail-msp09:20:112
1663799345,22cyclictest12061-21ssh11:25:130
16653993323,8cyclictest0-21swapper/207:20:122
16653993313,14cyclictest22146irq/40-dwc2_hso11:40:142
1665399331,22cyclictest8126-21sh09:35:132
1663799334,20cyclictest12-21ksoftirqd/007:50:130
16637993314,16cyclictest12-21ksoftirqd/007:45:120
16637993310,17cyclictest13152-21sendmail-msp07:40:130
16653993221,7cyclictest261rcuc/208:25:122
1665399321,18cyclictest15041-21sendmail-msp09:40:132
1665399312,24cyclictest27855-21ssh11:58:322
1664599312,21cyclictest3975-21ssh10:15:101
1663799314,23cyclictest1-21systemd07:15:110
1663799312,23cyclictest8175-21ssh10:38:320
1665399303,18cyclictest22146irq/40-dwc2_hso07:35:112
1665399303,16cyclictest22146irq/40-dwc2_hso11:50:122
1663799302,20cyclictest18303-21ssh09:20:130
1666199293,14cyclictest25866irq/58-eth007:15:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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