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2025-06-19 - 17:09

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Thu Jun 19, 2025 12:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
866099961,29cyclictest12-21ksoftirqd/012:35:120
866099541,38cyclictest28843-21ssh10:40:170
866099538,7cyclictest131rcu_preempt08:10:130
8660994714,18cyclictest12-21ksoftirqd/009:25:130
868899466,24cyclictest32466irq/58-eth012:25:123
866099453,8cyclictest12-21ksoftirqd/007:30:170
8680994421,15cyclictest27-21ksoftirqd/211:00:152
866099441,34cyclictest1977-21ssh09:15:130
868899431,22cyclictest32466irq/58-eth012:15:133
8668994212,5cyclictest131rcu_preempt12:25:131
866099413,22cyclictest11435-21ssh10:50:150
8660994128,7cyclictest12-21ksoftirqd/009:45:150
866899401,31cyclictest1257-21ssh11:05:151
868899392,24cyclictest32466irq/58-eth009:35:173
8660993924,8cyclictest121ksoftirqd/011:30:130
8660993924,8cyclictest121ksoftirqd/011:30:130
866099384,19cyclictest131rcu_preempt11:50:140
868099372,24cyclictest9620-21ssh10:05:152
866099362,4cyclictest131rcu_preempt08:20:160
8688993511,13cyclictest32466irq/58-eth009:45:163
8680993515,15cyclictest0-21swapper/210:10:142
8680993510,7cyclictest131rcu_preempt12:16:122
866099352,6cyclictest131rcu_preempt12:20:160
866899349,3cyclictest131rcu_preempt12:30:151
868099333,21cyclictest30886-21ssh11:45:152
868099331,18cyclictest14510-21sh11:35:122
866099331,27cyclictest9370-21ssh09:20:150
868899324,19cyclictest32466irq/58-eth010:10:133
868899318,9cyclictest0-21swapper/310:55:163
868099311,18cyclictest18617-21ssh10:55:182
866099311,22cyclictest23838-21sh11:20:120
868099302,18cyclictest13646-21ssh09:45:152
8680993019,9cyclictest27-21ksoftirqd/208:10:122
868099294,17cyclictest23346irq/40-dwc2_hso09:10:162
868099292,20cyclictest0-21swapper/207:20:172
866099296,13cyclictest31849-21kworker/0:012:25:130
866099290,20cyclictest14582-21ssh11:55:140
868899282,13cyclictest32466irq/58-eth008:10:133
868099283,19cyclictest0-21swapper/212:14:462
868099283,18cyclictest0-21swapper/207:15:142
868099283,18cyclictest0-21swapper/207:15:132
868099283,11cyclictest27-21ksoftirqd/212:33:212
868099282,20cyclictest0-21swapper/210:50:452
868099282,19cyclictest0-21swapper/211:08:452
8668992810,3cyclictest21-21ksoftirqd/109:50:011
866099289,14cyclictest12-21ksoftirqd/007:25:150
868899273,18cyclictest0-21swapper/312:22:453
868899273,17cyclictest0-21swapper/310:39:463
868899272,18cyclictest0-21swapper/312:13:463
8688992716,7cyclictest32466irq/58-eth011:15:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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