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2024-04-26 - 00:58

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Thu Apr 25, 2024 12:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2117199591,32cyclictest21438-21ssh11:35:132
21183995529,23cyclictest26866irq/58-eth009:20:113
2114899511,34cyclictest32453-21ssh10:05:130
2118399403,26cyclictest26866irq/58-eth008:30:113
2118399403,24cyclictest26866irq/58-eth012:10:133
2118399394,18cyclictest26866irq/58-eth011:45:133
2118399394,18cyclictest26866irq/58-eth011:45:133
2118399382,24cyclictest26866irq/58-eth009:35:143
2118399373,18cyclictest26866irq/58-eth010:10:143
2118399372,21cyclictest26866irq/58-eth012:35:123
21183993719,9cyclictest26866irq/58-eth011:00:123
21183993719,9cyclictest26866irq/58-eth011:00:123
2117199378,16cyclictest27-21ksoftirqd/208:35:332
2118399364,22cyclictest33-21ksoftirqd/308:55:113
2118399362,18cyclictest26866irq/58-eth012:15:133
2114899353,6cyclictest12-21ksoftirqd/010:00:120
2117199339,17cyclictest27-21ksoftirqd/209:30:202
2117199339,15cyclictest27-21ksoftirqd/210:48:482
21171993316,11cyclictest27-21ksoftirqd/207:25:222
21148993320,7cyclictest12-21ksoftirqd/012:15:250
2117199329,15cyclictest27-21ksoftirqd/212:30:222
2117199328,16cyclictest27-21ksoftirqd/209:25:282
2117199328,14cyclictest0-21swapper/210:04:252
2117199327,13cyclictest27-21ksoftirqd/209:50:352
2117199326,13cyclictest27-21ksoftirqd/207:45:212
2117199325,20cyclictest27-21ksoftirqd/211:50:022
2117199325,20cyclictest27-21ksoftirqd/211:50:012
21171993211,15cyclictest0-21swapper/210:05:372
21171993210,9cyclictest0-21swapper/212:20:132
2118399313,18cyclictest26866irq/58-eth010:00:123
21183993117,8cyclictest26866irq/58-eth011:35:133
2117199316,14cyclictest27-21ksoftirqd/209:20:142
21171993115,8cyclictest27-21ksoftirqd/211:25:212
21171993113,9cyclictest27-21ksoftirqd/210:10:332
21171993113,3cyclictest92-21pr/ttyS008:00:012
21171993111,7cyclictest0-21swapper/211:52:592
21171993111,14cyclictest0-21swapper/212:11:582
21171993111,11cyclictest0-21swapper/211:16:222
21171993110,15cyclictest0-21swapper/212:19:492
21171993110,15cyclictest0-21swapper/211:56:052
2116099314,4cyclictest21-21ksoftirqd/111:50:311
21148993117,5cyclictest12-21ksoftirqd/009:26:090
2118399309,14cyclictest26866irq/58-eth008:15:123
2117199309,15cyclictest0-21swapper/210:32:152
2117199308,4cyclictest27-21ksoftirqd/212:06:192
2117199308,4cyclictest27-21ksoftirqd/210:19:552
2117199308,4cyclictest27-21ksoftirqd/210:19:552
2117199308,15cyclictest0-21swapper/211:30:342
2117199307,8cyclictest27-21ksoftirqd/209:44:582
2117199305,15cyclictest27-21ksoftirqd/207:10:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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