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2026-03-17 - 09:40

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Tue Mar 17, 2026 00:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3040599639,7cyclictest131rcu_preempt23:05:120
30430995312,27cyclictest28366irq/58-eth022:15:143
30422994822,22cyclictest131rcu_preempt00:25:132
3040599484,34cyclictest22472-21ssh23:55:120
3040599484,34cyclictest22472-21ssh23:55:120
3040599483,7cyclictest131rcu_preempt23:30:130
3040599483,34cyclictest11275-21ssh21:25:130
3042299452,22cyclictest27-21ksoftirqd/200:35:132
3040599441,32cyclictest8023-21ssh22:35:120
3043099438,25cyclictest28366irq/58-eth021:25:123
30405994315,21cyclictest12-21ksoftirqd/019:45:120
3042299421,35cyclictest855-21ssh23:25:132
3042299421,35cyclictest855-21ssh23:25:132
3040599402,31cyclictest22331-21ssh22:25:130
3042299391,11cyclictest131rcu_preempt20:05:112
3040599391,29cyclictest20290-21ssh21:30:120
3042299384,17cyclictest0-21swapper/223:55:122
3042299384,17cyclictest0-21swapper/223:55:122
3041499381,33cyclictest26060-21ssh00:15:151
3040599388,9cyclictest12-21ksoftirqd/022:50:140
3043099378,16cyclictest28366irq/58-eth022:20:133
3042299372,29cyclictest4930-21rm21:39:232
30422993713,21cyclictest27-21ksoftirqd/221:45:142
3040599371,29cyclictest25681-21sh21:15:120
3042299362,17cyclictest27466-21rm21:50:232
3042299355,20cyclictest0-21swapper/223:40:142
3042299352,28cyclictest27596-21ssh22:10:122
3042299344,15cyclictest15312-21ssh23:15:132
3042299341,15cyclictest4523-21ssh23:45:142
30414993429,3cyclictest0-21swapper/121:15:111
3040599343,27cyclictest7961-21ssh00:05:100
3040599341,24cyclictest20631-21ssh00:30:140
3040599341,24cyclictest20631-21ssh00:30:140
30414993216,5cyclictest21-21ksoftirqd/122:05:111
3042299312,21cyclictest11736-21ssh22:55:142
3042299312,21cyclictest11736-21ssh22:55:142
3043099301,20cyclictest28466irq/59-eth022:05:113
3042299302,14cyclictest29662-21ssh23:05:132
3041499306,16cyclictest13491-21ssh23:50:131
3040599302,22cyclictest12273-21sh21:42:250
3042299298,10cyclictest0-21swapper/221:55:132
3042299293,18cyclictest22346irq/40-dwc2_hso20:10:122
3042299293,14cyclictest0-21swapper/223:20:132
3042299292,14cyclictest31489-21ssh00:00:142
3042299292,11cyclictest29684-21ntp_192.168.11422:45:232
3042299283,14cyclictest22346irq/40-dwc2_hso19:10:132
3042299282,20cyclictest22346irq/40-dwc2_hso22:50:132
3042299282,11cyclictest29608-21ssh22:28:232
30422992818,5cyclictest0-21swapper/222:00:142
3041499282,22cyclictest7425-21ssh23:27:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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