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2026-04-18 - 15:03

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Sat Apr 18, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
616129078,8sleep20-21swapper/207:06:082
615429068,17sleep00-21swapper/007:06:010
640228659,21sleep10-21swapper/107:09:161
635228471,9sleep30-21swapper/307:08:383
655799280,28cyclictest0-21swapper/211:37:152
655399275,21cyclictest0-21swapper/112:35:131
655799260,26cyclictest0-21swapper/212:01:152
655799240,1cyclictest0-21swapper/212:05:202
655799240,0cyclictest0-21swapper/209:10:002
655799230,23cyclictest0-21swapper/211:59:352
655399230,1cyclictest0-21swapper/111:44:031
655799220,22cyclictest0-21swapper/212:24:412
655799220,19cyclictest0-21swapper/211:18:062
655799210,21cyclictest0-21swapper/209:56:202
655799210,0cyclictest0-21swapper/210:43:272
655799200,20cyclictest0-21swapper/212:38:122
655799200,20cyclictest0-21swapper/211:32:492
655799200,20cyclictest0-21swapper/209:37:052
655399200,1cyclictest0-21swapper/111:53:571
655999190,19cyclictest0-21swapper/312:36:323
655799190,19cyclictest0-21swapper/209:46:312
655399190,15cyclictest0-21swapper/109:10:171
655199191,13cyclictest0-21swapper/010:45:120
655999180,1cyclictest0-21swapper/312:07:053
655999180,14cyclictest0-21swapper/310:58:513
655799180,1cyclictest0-21swapper/212:27:562
6553991817,1cyclictest0-21swapper/109:36:361
655399180,17cyclictest0-21swapper/112:19:491
655199180,1cyclictest0-21swapper/011:09:190
655199180,18cyclictest0-21swapper/011:35:120
89402170,0sleep30-21swapper/309:15:183
655999170,3cyclictest0-21swapper/311:30:103
655999170,16cyclictest0-21swapper/311:04:293
655799170,3cyclictest0-21swapper/210:03:152
6553991715,2cyclictest0-21swapper/111:39:311
655399170,16cyclictest0-21swapper/109:43:431
655199174,7cyclictest7528-21awk09:15:010
655999165,3cyclictest141rcu_preempt11:25:273
655799160,8cyclictest0-21swapper/210:15:002
6553991615,1cyclictest0-21swapper/111:15:281
6553991615,1cyclictest0-21swapper/110:08:101
655399160,1cyclictest0-21swapper/112:14:281
655399160,1cyclictest0-21swapper/110:23:491
655199160,16cyclictest0-21swapper/009:23:310
655999153,5cyclictest0-21swapper/310:20:573
6557991514,1cyclictest0-21swapper/211:51:402
6557991514,1cyclictest0-21swapper/210:33:342
6557991510,2cyclictest24668-21head11:20:212
655799150,15cyclictest0-21swapper/209:19:392
655399150,1cyclictest0-21swapper/111:10:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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