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2024-06-20 - 03:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot0.osadl.org (updated Wed Jun 19, 2024 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6620
"cycles":100000000,6619
"load":"idle",6618
"condition":{6617
"clock":"2300"6615
"family":"x86",6614
"vendor":"Intel",6613
"processor":{6611
"dataset":"2024-01-08T15:38:01+01:00"6609
"origin":"2024-01-08T12:43:21+01:00",6608
"timestamps":{6607
"granularity":"microseconds"6605
2300:51:066603
23,00:51:066602
31,00:51:146601
28,00:51:116600
"maxima":[6599
000:50:436596
0,00:50:436595
0,00:50:436594
0,00:50:436593
0,00:50:436592
0,00:50:436591
0,00:50:436590
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0,00:50:436579
0,00:50:436578
0,00:50:436577
0,00:50:436576
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0,00:50:436574
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0,00:50:436570
0,00:50:436569
0,00:50:436568
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0,00:50:436563
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0,00:50:436559
0,00:50:436558
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0,00:50:436514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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