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2026-05-11 - 16:57

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot2s.osadl.org (updated Mon May 11, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2784346998261,18cyclictest86-21hwrng09:48:453
2784346998261,18cyclictest86-21hwrng09:48:453
2784346997969,7cyclictest86-21hwrng12:22:213
2784346997969,7cyclictest86-21hwrng12:22:213
2784346997667,6cyclictest86-21hwrng11:12:433
2784346997667,6cyclictest86-21hwrng11:12:433
2784346997667,6cyclictest86-21hwrng08:17:373
2784346997468,4cyclictest86-21hwrng08:12:303
2784346997366,5cyclictest86-21hwrng07:41:473
2784346997365,6cyclictest86-21hwrng07:28:283
2784346997063,5cyclictest86-21hwrng10:36:533
2784346997063,5cyclictest86-21hwrng10:36:533
2784346997063,5cyclictest86-21hwrng07:38:423
2784346997062,5cyclictest86-21hwrng08:51:243
2784343997061,4cyclictest86-21hwrng10:35:510
2784343997061,4cyclictest86-21hwrng10:35:510
2784346996962,5cyclictest86-21hwrng07:15:093
2784343996919,35cyclictest2882605-21ssh10:40:220
2784344996861,4cyclictest0-21swapper/110:35:511
2784344996861,4cyclictest0-21swapper/110:35:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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