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2024-07-21 - 06:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 2 SMIs that occured during the measurement.
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot2.osadl.org (updated Sun Jul 21, 2024 00:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,7247
"cycles":100000000,7246
"load":"idle",7245
"condition":{7244
"clock":"2100"7242
"family":"x86",7241
"vendor":"Intel",7240
"processor":{7238
"dataset":"2024-01-08T15:38:33+01:00"7236
"origin":"2024-01-08T12:43:31+01:00",7235
"timestamps":{7234
"granularity":"microseconds"7232
5011:29:147230
132,11:30:367229
31,11:28:557228
109,11:30:137227
"maxima":[7226
011:28:247223
0,11:28:247222
0,11:28:247221
0,11:28:247220
0,11:28:247219
0,11:28:247218
0,11:28:247217
0,11:28:247216
0,11:28:247215
0,11:28:247214
0,11:28:247213
0,11:28:247212
0,11:28:247211
0,11:28:247210
0,11:28:247209
0,11:28:247208
0,11:28:247207
0,11:28:247206
0,11:28:247205
0,11:28:247204
0,11:28:247203
0,11:28:247202
0,11:28:247201
0,11:28:247200
0,11:28:247199
0,11:28:247198
0,11:28:247197
0,11:28:247196
0,11:28:247195
0,11:28:247194
0,11:28:247193
0,11:28:247192
0,11:28:247191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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