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2023-03-24 - 17:33

x86 Intel Core i3-2310E @2100 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #8, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by a total of 2 SMIs that occured during the measurement.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot2.osadl.org (updated Fri Mar 24, 2023 12:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2509799119117,1cyclictest0-21swapper/007:11:540
25100999794,1cyclictest3163-21strings07:32:063
25097996057,2cyclictest12-21ksoftirqd/007:32:060
80542400,1sleep30-21swapper/310:06:223
25098993325,7cyclictest0-21swapper/107:11:541
92102310,1sleep20-21swapper/210:07:012
25100992923,2cyclictest5019-21df_inode08:52:003
25100992923,2cyclictest5019-21df_inode08:52:003
2510099291,27cyclictest0-21swapper/307:17:003
23862270,0sleep20-21swapper/209:31:422
150412260,0sleep10-21swapper/109:42:071
40612250,0sleep00-21swapper/010:32:000
40612250,0sleep00-21swapper/010:32:000
240862240,1sleep00-21swapper/010:20:500
2509899230,21cyclictest0-21swapper/111:07:051
2509999220,21cyclictest0-21swapper/211:27:022
2509799221,20cyclictest0-21swapper/010:06:580
187202220,0sleep00-21swapper/009:16:490
2510099204,5cyclictest141rcu_preempt09:32:403
2509899190,1cyclictest0-21swapper/108:06:581
249952194,11sleep20-21swapper/207:11:472
275402180,0sleep30-21swapper/309:24:133
2510099165,8cyclictest0-21swapper/308:50:123
2510099163,5cyclictest141rcu_preempt09:46:523
2510099163,3cyclictest141rcu_preempt10:32:053
2510099163,3cyclictest141rcu_preempt10:32:053
25100991610,2cyclictest17692-21df08:07:003
2509799161,8cyclictest18916-21munin-run09:46:460
2510099154,5cyclictest141rcu_preempt11:11:233
2510099152,5cyclictest141rcu_preempt12:00:473
2509799155,5cyclictest0-21swapper/012:23:410
2509799155,5cyclictest0-21swapper/009:59:460
2510099147,5cyclictest0-21swapper/311:42:523
2510099144,5cyclictest29071-21ssh12:23:133
2510099144,5cyclictest0-21swapper/309:28:003
2510099143,6cyclictest11052-21/usr/sbin/munin12:07:053
2510099143,6cyclictest0-21swapper/309:18:083
2510099143,2cyclictest141rcu_preempt07:37:043
2510099142,3cyclictest141rcu_preempt11:52:133
2510099142,2cyclictest141rcu_preempt07:22:023
2510099141,5cyclictest141rcu_preempt09:57:353
2510099140,5cyclictest141rcu_preempt12:21:373
2509999145,4cyclictest6361-21ssh10:04:072
2509999144,8cyclictest13411-21ssh11:39:312
2509999143,9cyclictest27149-21ssh12:22:022
2509999143,7cyclictest0-21swapper/209:17:182
2509799144,8cyclictest5496-21ssh12:02:030
2509799144,5cyclictest0-21swapper/011:20:030
2509799140,8cyclictest25105-21perf10:51:470
250552143,8sleep30-21swapper/307:11:483
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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