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2024-06-17 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack8slot3.osadl.org (updated Mon Jun 17, 2024 13:10:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5103
"cycles":100000000,5102
"load":"idle",5101
"condition":{5100
"clock":"2667"5098
"family":"x86",5097
"vendor":"Intel",5096
"processor":{5094
"dataset":"2024-01-08T03:37:02+0100"5092
"origin":"2024-01-08T00:43:21+0100",5091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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