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2021-07-29 - 03:37

Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot3.osadl.org (updated Thu Jul 29, 2021 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179252182108,69sleep30-21swapper/319:05:543
181012181160,17sleep20-21swapper/219:07:582
164442177105,68sleep00-21swapper/019:05:030
181272120101,15sleep10-21swapper/119:08:171
2898521070,2sleep11852599cyclictest23:48:061
195182910,8sleep30-21swapper/321:25:263
163622900,3sleep10-21swapper/100:08:201
323542880,7sleep30-21swapper/322:45:173
59042860,5sleep30-21swapper/300:30:163
1852699363,32cyclictest0-21swapper/219:18:392
1852699318,22cyclictest0-21swapper/222:37:032
1852699313,26cyclictest0-21swapper/222:06:552
1852599315,25cyclictest0-21swapper/123:20:221
1852599315,25cyclictest0-21swapper/121:35:201
1852599315,25cyclictest0-21swapper/120:10:211
1852599315,25cyclictest0-21swapper/119:18:381
18525993116,14cyclictest0-21swapper/122:12:091
1852699308,21cyclictest0-21swapper/223:30:212
1852699307,22cyclictest0-21swapper/221:32:272
1852699304,24cyclictest0-21swapper/200:12:282
1852599306,23cyclictest0-21swapper/123:35:201
1852699295,23cyclictest0-21swapper/223:19:012
1852699295,23cyclictest0-21swapper/200:32:092
1852699295,23cyclictest0-21swapper/200:20:002
1852699294,24cyclictest0-21swapper/223:50:332
1852699293,24cyclictest0-21swapper/200:09:372
1852599296,22cyclictest0-21swapper/121:17:451
1852599295,23cyclictest0-21swapper/121:49:411
1852599295,23cyclictest0-21swapper/120:24:541
1852599295,23cyclictest0-21swapper/100:20:191
1852599295,23cyclictest0-21swapper/100:00:241
18524992917,11cyclictest0-21swapper/000:15:570
1852699286,21cyclictest0-21swapper/223:24:412
1852699286,21cyclictest0-21swapper/222:56:012
1852699286,21cyclictest0-21swapper/222:22:102
1852699286,21cyclictest0-21swapper/221:15:292
1852699285,22cyclictest0-21swapper/223:47:502
1852699285,22cyclictest0-21swapper/222:29:312
1852699285,22cyclictest0-21swapper/222:17:312
1852699285,22cyclictest0-21swapper/221:55:182
1852699285,21cyclictest0-21swapper/222:00:572
1852699284,22cyclictest0-21swapper/200:36:462
1852699283,24cyclictest0-21swapper/223:43:542
1852699283,24cyclictest0-21swapper/200:25:372
1852699283,23cyclictest0-21swapper/221:35:542
1852599286,21cyclictest0-21swapper/123:30:561
1852599285,22cyclictest0-21swapper/122:56:311
1852599282,25cyclictest0-21swapper/122:20:201
18525992815,12cyclictest0-21swapper/122:16:191
18524992812,15cyclictest0-21swapper/023:48:220
18527992713,13cyclictest0-21swapper/322:29:243
1852699276,20cyclictest0-21swapper/223:11:012
1852699276,20cyclictest0-21swapper/222:45:522
1852699274,22cyclictest0-21swapper/223:35:202
1852699274,22cyclictest0-21swapper/222:10:222
1852699274,22cyclictest0-21swapper/220:20:202
1852699274,21cyclictest0-21swapper/223:05:002
1852699273,22cyclictest0-21swapper/222:32:282
18526992715,11cyclictest0-21swapper/223:58:342
18526992715,11cyclictest0-21swapper/223:28:282
18526992715,11cyclictest0-21swapper/221:46:052
18526992715,11cyclictest0-21swapper/221:26:262
18526992715,11cyclictest0-21swapper/221:21:122
18526992715,11cyclictest0-21swapper/200:20:382
1852599277,19cyclictest0-21swapper/123:19:471
1852599276,20cyclictest0-21swapper/123:00:201
1852599275,21cyclictest0-21swapper/123:59:511
1852599275,21cyclictest0-21swapper/123:08:021
1852599275,21cyclictest0-21swapper/122:41:141
1852599274,22cyclictest0-21swapper/123:12:091
1852599274,22cyclictest0-21swapper/122:06:541
1852599274,22cyclictest0-21swapper/121:40:491
1852599274,22cyclictest0-21swapper/121:26:081
1852599273,23cyclictest0-21swapper/100:13:281
18525992715,11cyclictest0-21swapper/122:50:511
18525992715,11cyclictest0-21swapper/122:39:511
18525992715,11cyclictest0-21swapper/122:25:191
18524992714,12cyclictest7158-21latency_hist22:19:590
18524992713,13cyclictest212050irq/31-eth023:29:380
18524992713,13cyclictest212050irq/31-eth021:14:480
276112260,9sleep30-21swapper/323:13:443
18527992614,11cyclictest0-21swapper/323:34:363
18527992611,14cyclictest80572sleep321:47:133
1852699264,21cyclictest0-21swapper/221:13:022
1852699263,22cyclictest0-21swapper/223:00:202
1852699263,22cyclictest0-21swapper/220:35:232
1852699263,22cyclictest0-21swapper/220:10:212
1852699263,22cyclictest0-21swapper/200:00:242
1852599266,20cyclictest0-21swapper/123:41:131
1852599266,19cyclictest0-21swapper/123:28:251
1852599266,19cyclictest0-21swapper/121:51:451
1852599264,21cyclictest0-21swapper/123:50:281
1852599263,22cyclictest0-21swapper/122:45:311
1852599263,22cyclictest0-21swapper/121:12:381
1852599263,21cyclictest0-21swapper/100:25:241
1852599262,23cyclictest0-21swapper/100:15:181
18525992618,8cyclictest0-21swapper/100:32:441
18525992616,9cyclictest0-21swapper/121:24:481
18524992615,9cyclictest212050irq/31-eth021:54:140
18524992615,10cyclictest0-21swapper/021:48:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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