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2022-10-04 - 01:48

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot3.osadl.org (updated Mon Oct 03, 2022 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235622221105,111sleep30-21swapper/307:09:253
233792178159,15sleep10-21swapper/107:07:191
232922176157,15sleep20-21swapper/207:06:192
23554215079,67sleep00-21swapper/007:09:180
23865993115,15cyclictest0-21swapper/112:29:311
2386699286,20cyclictest0-21swapper/212:35:202
2386699286,20cyclictest0-21swapper/212:35:192
23865992816,11cyclictest0-21swapper/109:23:571
23865992812,8cyclictest0-21swapper/111:20:131
2386699275,21cyclictest0-21swapper/209:58:262
2386699274,22cyclictest0-21swapper/211:52:442
2386599274,22cyclictest0-21swapper/109:46:091
23865992716,10cyclictest0-21swapper/110:04:571
135032270,1sleep10-21swapper/110:50:531
2386799268,17cyclictest0-21swapper/312:15:003
2386699266,19cyclictest0-21swapper/210:55:332
2386699265,20cyclictest0-21swapper/212:33:552
2386699265,20cyclictest0-21swapper/211:23:312
2386699265,20cyclictest0-21swapper/209:24:042
2386699265,19cyclictest0-21swapper/212:25:462
2386599265,20cyclictest0-21swapper/112:00:241
2386599265,20cyclictest0-21swapper/110:37:501
2386599265,20cyclictest0-21swapper/110:08:321
23865992614,11cyclictest0-21swapper/110:11:561
23865992613,12cyclictest0-21swapper/110:29:461
23865992612,13cyclictest0-21swapper/111:05:391
23865992612,13cyclictest0-21swapper/109:26:091
2386699256,19cyclictest0-21swapper/212:23:122
2386699256,18cyclictest0-21swapper/212:10:122
2386699255,19cyclictest0-21swapper/211:57:592
2386699255,19cyclictest0-21swapper/211:48:212
2386699255,19cyclictest0-21swapper/211:35:052
2386699255,19cyclictest0-21swapper/211:19:372
2386699255,19cyclictest0-21swapper/210:12:292
2386699255,19cyclictest0-21swapper/209:25:532
2386699255,19cyclictest0-21swapper/209:19:292
23866992516,8cyclictest0-21swapper/210:28:542
23865992515,9cyclictest0-21swapper/112:32:061
23865992515,9cyclictest0-21swapper/112:17:061
23865992515,9cyclictest0-21swapper/112:10:261
23865992515,9cyclictest0-21swapper/111:49:511
23865992515,9cyclictest0-21swapper/111:40:251
23865992515,9cyclictest0-21swapper/111:29:111
23865992515,9cyclictest0-21swapper/111:15:291
23865992515,9cyclictest0-21swapper/110:55:271
23865992515,9cyclictest0-21swapper/110:46:461
23865992515,9cyclictest0-21swapper/110:21:101
23865992515,9cyclictest0-21swapper/110:15:171
23865992515,9cyclictest0-21swapper/109:42:011
23865992515,9cyclictest0-21swapper/109:37:291
23865992515,9cyclictest0-21swapper/109:10:191
23865992515,9cyclictest0-21swapper/109:09:591
23865992515,9cyclictest0-21swapper/109:02:161
23865992515,9cyclictest0-21swapper/107:37:291
23865992514,10cyclictest0-21swapper/112:36:041
23865992514,10cyclictest0-21swapper/112:36:031
23865992514,10cyclictest0-21swapper/112:24:001
23865992514,10cyclictest0-21swapper/111:51:221
23865992514,10cyclictest0-21swapper/111:35:081
23865992514,10cyclictest0-21swapper/111:30:051
23865992514,10cyclictest0-21swapper/111:12:491
23865992514,10cyclictest0-21swapper/111:00:341
23865992514,10cyclictest0-21swapper/110:40:491
23865992514,10cyclictest0-21swapper/109:55:561
23865992514,10cyclictest0-21swapper/109:31:521
23865992514,10cyclictest0-21swapper/109:17:091
23865992512,12cyclictest0-21swapper/109:50:061
3017422415,7sleep30-21swapper/310:03:503
2386799248,15cyclictest0-21swapper/309:24:293
2386699246,17cyclictest0-21swapper/210:31:122
2386699245,19cyclictest0-21swapper/209:37:372
2386699245,18cyclictest0-21swapper/211:40:282
2386699245,18cyclictest0-21swapper/211:10:202
2386699245,18cyclictest0-21swapper/210:02:232
2386699245,18cyclictest0-21swapper/209:50:052
2386699244,19cyclictest0-21swapper/212:15:172
2386699244,19cyclictest0-21swapper/210:53:512
2386699244,19cyclictest0-21swapper/210:48:182
2386699244,19cyclictest0-21swapper/210:16:412
2386699244,19cyclictest0-21swapper/209:43:312
2386699242,21cyclictest0-21swapper/210:40:412
23866992415,8cyclictest0-21swapper/212:05:282
23866992415,8cyclictest0-21swapper/211:31:112
23866992415,8cyclictest0-21swapper/210:20:252
23866992415,8cyclictest0-21swapper/210:05:512
23866992415,8cyclictest0-21swapper/209:45:192
23866992415,8cyclictest0-21swapper/209:32:412
23866992415,8cyclictest0-21swapper/209:10:022
23866992415,8cyclictest0-21swapper/209:05:242
23866992415,8cyclictest0-21swapper/208:40:202
23866992414,9cyclictest0-21swapper/210:36:062
23866992413,10cyclictest0-21swapper/211:27:402
23865992415,8cyclictest0-21swapper/107:30:191
23865992414,9cyclictest0-21swapper/112:08:361
23865992414,9cyclictest0-21swapper/111:55:171
23865992414,9cyclictest0-21swapper/108:55:261
23865992414,9cyclictest0-21swapper/108:50:201
23865992414,9cyclictest0-21swapper/108:05:211
23865992414,9cyclictest0-21swapper/107:20:171
23865992413,10cyclictest0-21swapper/110:31:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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