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2022-05-27 - 16:55

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot3.osadl.org (updated Fri May 27, 2022 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291972182163,15sleep20-21swapper/207:05:042
306822180108,67sleep30-21swapper/307:06:023
309282177159,14sleep10-21swapper/107:08:511
307382168105,59sleep00-21swapper/007:06:390
84252890,3sleep20-21swapper/212:06:202
3127799289,18cyclictest0-21swapper/210:56:352
3127799279,17cyclictest0-21swapper/211:42:312
3127799273,23cyclictest0-21swapper/211:08:542
3127799268,17cyclictest0-21swapper/212:01:062
3127799266,19cyclictest0-21swapper/210:30:192
3127799266,19cyclictest0-21swapper/209:22:472
3127899259,15cyclictest0-21swapper/310:13:323
3127799258,16cyclictest0-21swapper/211:10:342
3127799258,16cyclictest0-21swapper/211:01:472
3127799256,18cyclictest0-21swapper/211:28:492
3127799255,19cyclictest0-21swapper/211:30:212
3127799255,19cyclictest0-21swapper/210:48:262
3127799255,19cyclictest0-21swapper/210:24:582
3127799255,19cyclictest0-21swapper/209:51:002
3127799255,19cyclictest0-21swapper/209:19:532
3127799254,20cyclictest0-21swapper/212:31:032
3127799254,20cyclictest0-21swapper/212:18:402
3127799254,20cyclictest0-21swapper/210:18:232
31276992515,9cyclictest0-21swapper/110:19:591
31276992515,9cyclictest0-21swapper/107:45:081
3127899248,15cyclictest0-21swapper/310:18:593
3127899242,21cyclictest0-21swapper/309:35:303
3127899242,21cyclictest0-21swapper/309:26:043
3127799246,18cyclictest0-21swapper/211:16:392
3127799246,17cyclictest0-21swapper/210:51:202
3127799246,17cyclictest0-21swapper/210:09:252
3127799245,19cyclictest0-21swapper/209:59:462
3127799245,18cyclictest0-21swapper/212:25:132
3127799245,18cyclictest0-21swapper/210:00:162
3127799245,18cyclictest0-21swapper/209:44:212
3127799244,19cyclictest0-21swapper/210:38:062
3127799244,19cyclictest0-21swapper/210:27:462
3127799244,19cyclictest0-21swapper/209:33:102
3127799243,20cyclictest0-21swapper/212:37:102
3127799243,20cyclictest0-21swapper/211:52:092
3127799242,21cyclictest0-21swapper/210:11:242
3127699244,19cyclictest0-21swapper/111:51:001
31276992415,8cyclictest0-21swapper/109:50:191
31276992415,8cyclictest0-21swapper/108:53:581
31276992415,8cyclictest0-21swapper/107:50:231
31276992415,8cyclictest0-21swapper/107:30:231
2555822415,7sleep30-21swapper/312:26:173
3127899238,14cyclictest0-21swapper/310:44:483
3127899235,17cyclictest0-21swapper/309:47:053
3127899234,18cyclictest0-21swapper/312:13:183
3127899234,18cyclictest0-21swapper/311:36:203
3127899232,20cyclictest0-21swapper/311:42:413
3127899232,20cyclictest0-21swapper/310:46:153
3127899232,20cyclictest0-21swapper/309:17:293
31278992315,7cyclictest98392sleep312:08:583
31278992315,7cyclictest312802sleep307:10:023
31278992315,7cyclictest308932sleep311:18:363
31278992315,7cyclictest292302sleep308:20:263
31278992315,7cyclictest274592sleep310:36:353
31278992315,7cyclictest272082sleep309:21:583
31278992315,7cyclictest26022sleep310:09:003
31278992315,7cyclictest259472sleep309:58:143
31278992315,7cyclictest209042sleep311:06:023
31278992315,7cyclictest130012sleep307:43:023
31278992315,7cyclictest116842sleep309:40:483
31278992315,7cyclictest0-21swapper/312:25:003
31278992314,8cyclictest83062sleep311:30:063
31278992311,11cyclictest0-21swapper/312:38:363
3127799238,14cyclictest0-21swapper/212:11:292
3127799237,15cyclictest0-21swapper/209:35:532
3127799235,17cyclictest0-21swapper/210:40:362
3127799235,17cyclictest0-21swapper/209:25:322
3127799233,19cyclictest0-21swapper/211:35:122
3127799233,19cyclictest0-21swapper/211:20:252
3127799232,20cyclictest0-21swapper/212:20:182
3127799232,20cyclictest0-21swapper/209:46:452
3127799232,20cyclictest0-21swapper/209:10:472
3127799232,20cyclictest0-21swapper/209:10:462
31277992314,8cyclictest0-21swapper/207:55:012
3127699234,18cyclictest0-21swapper/112:16:361
3127699234,18cyclictest0-21swapper/111:11:251
3127699232,20cyclictest0-21swapper/112:35:481
3127699232,20cyclictest0-21swapper/110:56:001
3127699232,20cyclictest0-21swapper/109:12:161
3127699232,20cyclictest0-21swapper/109:12:161
31276992315,8cyclictest0-21swapper/112:06:301
31276992315,8cyclictest0-21swapper/111:59:031
31276992315,8cyclictest0-21swapper/111:31:431
31276992315,8cyclictest0-21swapper/109:57:111
31276992315,8cyclictest0-21swapper/109:25:221
31276992315,8cyclictest0-21swapper/108:55:131
31276992315,8cyclictest0-21swapper/107:20:171
31276992314,8cyclictest0-21swapper/112:30:191
31276992314,8cyclictest0-21swapper/112:29:121
31276992314,8cyclictest0-21swapper/112:00:241
31276992314,8cyclictest0-21swapper/111:38:221
31276992314,8cyclictest0-21swapper/110:45:171
31276992314,8cyclictest0-21swapper/110:33:271
31276992314,8cyclictest0-21swapper/110:20:221
31276992314,8cyclictest0-21swapper/110:00:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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