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2023-06-03 - 05:57

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot3.osadl.org (updated Sat Jun 03, 2023 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43722182108,69sleep30-21swapper/319:08:153
44622178161,13sleep10-21swapper/119:09:171
41682178160,14sleep20-21swapper/219:05:522
43942176108,64sleep00-21swapper/019:08:320
54372870,8sleep30-21swapper/323:01:093
229472770,5sleep30-21swapper/321:42:323
4718992910,19cyclictest0-21swapper/222:32:402
4713992922,6cyclictest0-21swapper/121:54:581
4713992922,6cyclictest0-21swapper/121:54:581
4713992918,11cyclictest0-21swapper/121:40:221
4713992916,12cyclictest0-21swapper/121:39:001
4703992915,13cyclictest5407-21sh21:57:040
4703992913,13cyclictest81rcu_preempt21:25:250
471899287,20cyclictest0-21swapper/221:49:472
471899287,20cyclictest0-21swapper/221:49:462
471399282,25cyclictest0-21swapper/121:58:481
4713992816,11cyclictest0-21swapper/122:18:151
4703992824,3cyclictest0-21swapper/023:52:070
4703992824,3cyclictest0-21swapper/022:24:230
4703992815,12cyclictest0-21swapper/021:13:360
471399275,21cyclictest0-21swapper/122:29:471
4713992715,11cyclictest0-21swapper/123:50:271
4713992715,11cyclictest0-21swapper/123:25:531
4713992715,11cyclictest0-21swapper/122:33:001
4713992715,11cyclictest0-21swapper/122:21:501
4713992715,11cyclictest0-21swapper/121:32:571
4713992715,11cyclictest0-21swapper/119:40:231
4713992715,11cyclictest0-21swapper/100:30:281
4713992715,11cyclictest0-21swapper/100:00:311
4713992714,9cyclictest0-21swapper/123:55:201
4703992723,3cyclictest23685-21nscd21:00:290
4703992722,3cyclictest81rcu_preempt23:35:260
4703992722,3cyclictest81rcu_preempt21:39:470
4703992721,5cyclictest0-21swapper/023:40:550
4703992717,3cyclictest3-21ksoftirqd/023:10:000
4703992713,13cyclictest3-21ksoftirqd/022:40:280
4703992712,3cyclictest81rcu_preempt21:21:400
61522260,6sleep30-21swapper/321:58:103
471899265,20cyclictest0-21swapper/222:40:222
471899264,21cyclictest0-21swapper/223:41:282
471899264,21cyclictest0-21swapper/222:09:472
471899264,21cyclictest0-21swapper/200:06:482
471899263,21cyclictest0-21swapper/222:26:462
4718992614,11cyclictest0-21swapper/222:02:292
4718992610,15cyclictest0-21swapper/200:21:502
471399269,16cyclictest0-21swapper/122:10:321
471399268,17cyclictest0-21swapper/121:25:091
471399268,17cyclictest0-21swapper/121:16:101
471399267,18cyclictest0-21swapper/123:32:171
471399265,20cyclictest0-21swapper/122:52:281
471399262,23cyclictest0-21swapper/123:09:451
4713992616,9cyclictest0-21swapper/123:46:031
4713992616,9cyclictest0-21swapper/123:43:561
4713992616,9cyclictest0-21swapper/123:20:051
4713992616,9cyclictest0-21swapper/122:55:281
4713992616,9cyclictest0-21swapper/122:46:131
4713992616,9cyclictest0-21swapper/122:09:401
4713992616,9cyclictest0-21swapper/120:40:211
4713992616,9cyclictest0-21swapper/119:10:191
4713992616,9cyclictest0-21swapper/100:37:501
4713992616,9cyclictest0-21swapper/100:14:271
4713992615,10cyclictest0-21swapper/123:14:201
4713992615,10cyclictest0-21swapper/122:41:371
4713992615,10cyclictest0-21swapper/122:01:041
4713992615,10cyclictest0-21swapper/121:47:261
4713992615,10cyclictest0-21swapper/121:47:251
4713992615,10cyclictest0-21swapper/121:20:131
4713992615,10cyclictest0-21swapper/120:17:041
4713992615,10cyclictest0-21swapper/100:20:481
4713992614,11cyclictest0-21swapper/123:00:271
4713992614,11cyclictest0-21swapper/121:12:161
4713992613,12cyclictest0-21swapper/120:22:001
4713992613,11cyclictest0-21swapper/121:00:241
4703992623,3cyclictest0-21swapper/022:45:200
4703992622,3cyclictest6640-21sh23:02:560
4703992622,3cyclictest3-21ksoftirqd/021:50:300
4703992622,3cyclictest3-21ksoftirqd/021:50:290
4703992619,4cyclictest81rcu_preempt23:20:230
4703992619,3cyclictest81rcu_preempt23:15:200
4703992618,6cyclictest216050irq/31-eth023:59:360
4703992618,6cyclictest216050irq/31-eth021:42:270
4703992617,6cyclictest81rcu_preempt20:00:150
4703992617,6cyclictest81rcu_preempt19:40:210
4703992616,7cyclictest81rcu_preempt19:10:190
4703992615,3cyclictest3-21ksoftirqd/022:10:250
4703992615,3cyclictest17005-21irqstats23:45:230
4703992613,3cyclictest0-21swapper/000:30:190
4703992612,3cyclictest81rcu_preempt22:50:300
4703992612,2cyclictest81rcu_preempt00:04:010
4703992611,2cyclictest81rcu_preempt23:10:210
76022515,9sleep30-21swapper/320:18:433
471899255,19cyclictest0-21swapper/221:30:202
471899255,19cyclictest0-21swapper/221:12:272
471899255,18cyclictest0-21swapper/222:12:332
471899253,21cyclictest0-21swapper/223:50:292
471899253,21cyclictest0-21swapper/222:38:212
471899253,21cyclictest0-21swapper/221:38:462
471899252,22cyclictest0-21swapper/221:42:152
471899252,22cyclictest0-21swapper/200:27:302
4718992511,13cyclictest2944-21qpidd00:13:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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