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2022-08-19 - 13:14

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack8slot3.osadl.org (updated Fri Aug 19, 2022 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117122268105,158sleep30-21swapper/319:09:053
113992183163,15sleep10-21swapper/119:05:311
114622178162,12sleep20-21swapper/219:06:132
115002174105,65sleep00-21swapper/019:06:420
640321030,5sleep30-21swapper/322:24:163
14592880,5sleep30-21swapper/321:15:003
191692850,3sleep236-21ksoftirqd/222:36:052
271612800,2sleep20-21swapper/200:21:182
12032994020,19cyclictest0-21swapper/123:57:351
12032993918,20cyclictest0-21swapper/122:32:151
12032993917,21cyclictest0-21swapper/100:14:551
12032993511,23cyclictest0-21swapper/100:38:271
12032993416,17cyclictest0-21swapper/123:34:241
12032993219,12cyclictest0-21swapper/122:39:381
12032993217,14cyclictest0-21swapper/122:42:221
12032993118,12cyclictest0-21swapper/121:19:261
1203399308,21cyclictest0-21swapper/221:43:352
12032993017,12cyclictest0-21swapper/121:20:111
12032993016,13cyclictest0-21swapper/122:29:171
1203399294,24cyclictest0-21swapper/221:33:522
12033992910,18cyclictest0-21swapper/223:10:122
1203299288,19cyclictest0-21swapper/120:00:201
12032992816,11cyclictest0-21swapper/123:51:001
12032992816,11cyclictest0-21swapper/123:45:181
12032992816,11cyclictest0-21swapper/123:40:171
12032992816,11cyclictest0-21swapper/123:38:581
12032992816,11cyclictest0-21swapper/123:29:171
12032992816,11cyclictest0-21swapper/123:20:041
12032992816,11cyclictest0-21swapper/123:15:321
12032992816,11cyclictest0-21swapper/123:13:011
12032992816,11cyclictest0-21swapper/123:00:061
12032992816,11cyclictest0-21swapper/122:58:291
12032992816,11cyclictest0-21swapper/122:51:341
12032992816,11cyclictest0-21swapper/122:48:261
12032992816,11cyclictest0-21swapper/122:21:581
12032992816,11cyclictest0-21swapper/122:15:071
12032992816,11cyclictest0-21swapper/122:12:081
12032992816,11cyclictest0-21swapper/122:05:561
12032992816,11cyclictest0-21swapper/121:50:521
12032992816,11cyclictest0-21swapper/121:36:311
12032992816,11cyclictest0-21swapper/121:31:021
12032992816,11cyclictest0-21swapper/121:10:481
12032992816,11cyclictest0-21swapper/120:11:481
12032992816,11cyclictest0-21swapper/100:31:171
12032992816,11cyclictest0-21swapper/100:28:461
12032992815,12cyclictest0-21swapper/121:49:341
12032992815,12cyclictest0-21swapper/100:20:221
12032992815,12cyclictest0-21swapper/100:03:281
12032992811,16cyclictest0-21swapper/122:01:401
1203499276,20cyclictest0-21swapper/322:36:013
1203499276,20cyclictest0-21swapper/320:50:203
1203399277,19cyclictest0-21swapper/223:40:312
1203399277,19cyclictest0-21swapper/222:22:112
1203399276,20cyclictest0-21swapper/223:45:562
1203399276,20cyclictest0-21swapper/223:30:492
1203399276,20cyclictest0-21swapper/221:47:472
1203399275,20cyclictest0-21swapper/221:36:432
1203399274,22cyclictest0-21swapper/221:59:552
1203399273,23cyclictest0-21swapper/200:10:072
1203399272,24cyclictest0-21swapper/200:32:142
12032992716,10cyclictest0-21swapper/123:05:451
12032992716,10cyclictest0-21swapper/121:56:311
12032992716,10cyclictest0-21swapper/121:25:101
12032992716,10cyclictest0-21swapper/121:05:141
12032992716,10cyclictest0-21swapper/121:00:191
12032992716,10cyclictest0-21swapper/120:51:051
12032992716,10cyclictest0-21swapper/120:30:141
12032992716,10cyclictest0-21swapper/120:25:211
12032992716,10cyclictest0-21swapper/120:20:251
12032992716,10cyclictest0-21swapper/120:18:051
12032992716,10cyclictest0-21swapper/119:55:181
12032992716,10cyclictest0-21swapper/119:40:211
12032992716,10cyclictest0-21swapper/119:35:121
12032992716,10cyclictest0-21swapper/119:15:231
12032992716,10cyclictest0-21swapper/119:10:121
12032992716,10cyclictest0-21swapper/100:17:531
12032992716,10cyclictest0-21swapper/100:06:261
1203499263,23cyclictest0-21swapper/320:00:203
12034992612,13cyclictest0-21swapper/300:04:343
1203399267,18cyclictest0-21swapper/223:01:212
1203399266,19cyclictest0-21swapper/222:45:212
1203399263,22cyclictest0-21swapper/222:09:112
1203399262,23cyclictest0-21swapper/221:12:292
12032992616,9cyclictest0-21swapper/119:50:231
12032992616,10cyclictest0-21swapper/120:45:161
12032992616,10cyclictest0-21swapper/120:35:241
12032992615,10cyclictest0-21swapper/121:40:091
12032992615,10cyclictest0-21swapper/119:25:151
1203399259,15cyclictest0-21swapper/223:24:512
1203399258,16cyclictest0-21swapper/223:06:282
1203399256,18cyclictest0-21swapper/223:52:132
1203399256,18cyclictest0-21swapper/222:16:302
1203399255,19cyclictest0-21swapper/222:04:292
1203399254,20cyclictest0-21swapper/223:16:412
1203399254,20cyclictest0-21swapper/222:31:492
1203399254,20cyclictest0-21swapper/200:26:442
1203399253,21cyclictest0-21swapper/221:26:072
1203399253,21cyclictest0-21swapper/221:18:062
1203399252,22cyclictest0-21swapper/223:35:052
1203399252,22cyclictest0-21swapper/200:16:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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