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2022-12-05 - 02:25

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack8slot3.osadl.org (updated Sun Dec 04, 2022 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295632206105,96sleep30-21swapper/307:05:023
311442177158,15sleep20-21swapper/207:07:052
310822177158,15sleep10-21swapper/107:06:241
310442169105,59sleep00-21swapper/007:05:550
224422930,1sleep022434-21needreboot11:25:180
186072790,1sleep20-21swapper/209:11:082
3164799332,30cyclictest0-21swapper/210:04:032
3164699308,21cyclictest0-21swapper/112:10:031
3164699308,21cyclictest0-21swapper/109:31:041
3164699298,20cyclictest0-21swapper/109:15:151
3164699297,21cyclictest0-21swapper/112:38:431
18492290,3sleep10-21swapper/111:05:161
31648992823,4cyclictest0-21swapper/311:56:543
31648992816,11cyclictest0-21swapper/309:54:483
3164699288,19cyclictest0-21swapper/111:16:211
3164699288,19cyclictest0-21swapper/110:11:491
3164799274,22cyclictest0-21swapper/211:37:032
3164799274,22cyclictest0-21swapper/211:12:012
3164799274,22cyclictest0-21swapper/211:03:122
3164699278,18cyclictest0-21swapper/112:20:121
3164699278,18cyclictest0-21swapper/110:30:101
3164699278,18cyclictest0-21swapper/110:30:101
3164699276,20cyclictest0-21swapper/111:56:211
3164699276,20cyclictest0-21swapper/111:29:491
3164699273,23cyclictest0-21swapper/110:53:081
3164699272,24cyclictest0-21swapper/109:46:131
31646992715,11cyclictest0-21swapper/110:57:481
31646992713,13cyclictest0-21swapper/111:38:091
31645992723,3cyclictest0-21swapper/010:16:550
31648992616,9cyclictest0-21swapper/312:35:443
3164799268,17cyclictest0-21swapper/211:28:322
31647992615,10cyclictest0-21swapper/211:16:402
31647992614,11cyclictest0-21swapper/211:32:072
3164699268,17cyclictest0-21swapper/109:57:071
3164699267,18cyclictest0-21swapper/112:28:581
3164699265,20cyclictest0-21swapper/111:32:581
3164699265,20cyclictest0-21swapper/111:01:111
3164699265,20cyclictest0-21swapper/110:42:551
3164699265,20cyclictest0-21swapper/110:36:561
3164699264,21cyclictest0-21swapper/112:04:531
31646992610,16cyclictest0-21swapper/110:25:071
31646992610,15cyclictest0-21swapper/110:00:191
31645992623,2cyclictest0-21swapper/012:09:140
31648992515,8cyclictest19095-21chrt12:26:493
31648992513,11cyclictest0-21swapper/312:05:573
31647992516,8cyclictest0-21swapper/209:50:132
3164699257,17cyclictest0-21swapper/109:41:361
3164699257,17cyclictest0-21swapper/109:26:381
3164699255,20cyclictest0-21swapper/110:17:051
3164699255,19cyclictest0-21swapper/112:19:311
3164699255,19cyclictest0-21swapper/111:23:081
3164699255,19cyclictest0-21swapper/110:06:071
3164699255,19cyclictest0-21swapper/109:52:001
3164699255,19cyclictest0-21swapper/109:38:231
3164699254,20cyclictest0-21swapper/111:40:181
3164699252,22cyclictest0-21swapper/112:34:481
3164699252,22cyclictest0-21swapper/110:47:101
31645992521,3cyclictest0-21swapper/012:14:180
186952250,8sleep30-21swapper/310:50:003
31648992416,7cyclictest0-21swapper/310:26:143
31648992416,7cyclictest0-21swapper/307:35:143
31648992415,8cyclictest68892sleep309:32:073
31648992415,8cyclictest0-21swapper/311:46:463
31648992415,8cyclictest0-21swapper/310:15:503
31648992414,9cyclictest0-21swapper/311:00:273
3164799244,19cyclictest0-21swapper/209:46:262
3164799242,21cyclictest0-21swapper/212:33:252
3164799242,21cyclictest0-21swapper/211:55:032
3164799242,21cyclictest0-21swapper/210:51:102
31647992415,8cyclictest0-21swapper/212:35:142
31647992415,8cyclictest0-21swapper/212:28:522
31647992415,8cyclictest0-21swapper/212:20:252
31647992415,8cyclictest0-21swapper/211:53:592
31647992415,8cyclictest0-21swapper/211:40:162
31647992415,8cyclictest0-21swapper/211:09:062
31647992415,8cyclictest0-21swapper/210:43:102
31647992415,8cyclictest0-21swapper/210:35:172
3164699244,19cyclictest0-21swapper/109:10:491
3164699243,20cyclictest0-21swapper/112:05:111
3164699243,20cyclictest0-21swapper/110:20:001
3164699242,21cyclictest0-21swapper/111:45:301
3164699242,21cyclictest0-21swapper/111:10:311
31646992415,8cyclictest0-21swapper/111:50:191
31646992415,8cyclictest0-21swapper/109:20:211
31646992415,8cyclictest0-21swapper/109:00:191
31646992415,8cyclictest0-21swapper/108:55:231
31646992415,8cyclictest0-21swapper/108:35:181
31646992415,8cyclictest0-21swapper/108:35:001
31646992415,8cyclictest0-21swapper/108:21:321
31646992415,8cyclictest0-21swapper/108:15:121
31646992415,8cyclictest0-21swapper/108:10:221
31646992415,8cyclictest0-21swapper/107:50:171
31646992415,8cyclictest0-21swapper/107:40:201
31646992415,8cyclictest0-21swapper/107:25:201
31646992415,8cyclictest0-21swapper/107:15:231
31646992414,9cyclictest0-21swapper/107:45:121
31645992421,3cyclictest215650irq/31-eth012:30:290
31645992415,8cyclictest26039-21diskmemload12:01:050
31645992414,3cyclictest0-21swapper/007:24:120
3164899235,17cyclictest0-21swapper/310:55:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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