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2019-07-24 - 00:11

Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack8slot3.osadl.org (updated Tue Jul 23, 2019 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182532227157,66sleep00-21swapper/007:09:010
179892227156,66sleep30-21swapper/307:05:593
171442183105,73sleep10-21swapper/107:05:081
179662180161,15sleep20-21swapper/207:05:412
1857799315,25cyclictest0-21swapper/107:10:111
1857799314,26cyclictest0-21swapper/110:15:231
18579992912,15cyclictest203172sleep308:29:053
1857799296,22cyclictest0-21swapper/109:20:121
1857799285,22cyclictest0-21swapper/110:05:181
18577992816,11cyclictest0-21swapper/110:30:051
18579992713,13cyclictest106332sleep310:43:523
18579992712,14cyclictest137582sleep308:12:353
1857899275,21cyclictest0-21swapper/209:00:122
1857899275,21cyclictest0-21swapper/209:00:122
1857899273,23cyclictest0-21swapper/210:15:232
1857799276,20cyclictest0-21swapper/109:00:121
1857799276,20cyclictest0-21swapper/109:00:111
1857799274,22cyclictest0-21swapper/111:56:361
1857799274,22cyclictest0-21swapper/108:55:121
1857799274,22cyclictest0-21swapper/108:55:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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