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2024-12-11 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Wed Dec 11, 2024 01:10:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5103
"cycles":100000000,5102
"load":"idle",5101
"condition":{5100
"clock":"2667"5098
"family":"x86",5097
"vendor":"Intel",5096
"processor":{5094
"dataset":"2024-01-08T03:37:02+0100"5092
"origin":"2024-01-08T00:43:21+0100",5091
"timestamps":{5090
"granularity":"microseconds"5088
3112:17:165086
48,12:16:465085
39,12:16:465084
23,12:16:465083
"maxima":[5082
012:16:465079
0,12:16:465078
0,12:16:465077
0,12:16:465076
0,12:16:465075
0,12:16:465074
0,12:16:465073
0,12:16:465072
0,12:16:465071
0,12:16:465070
0,12:16:465069
0,12:16:465068
0,12:16:465067
0,12:16:465066
0,12:16:465065
0,12:16:465064
0,12:16:465063
0,12:16:465062
0,12:16:465061
0,12:16:465060
0,12:16:465059
0,12:16:465058
0,12:16:465057
0,12:16:465056
0,12:16:465055
0,12:16:465054
0,12:16:465053
0,12:16:465052
0,12:16:465051
0,12:16:465050
0,12:16:465049
0,12:16:465048
0,12:16:465047
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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