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2021-01-21 - 06:34

Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Thu Jan 21, 2021 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137012182105,72sleep30-21swapper/319:06:353
139242179160,15sleep20-21swapper/219:09:052
137392179160,15sleep10-21swapper/119:06:571
135882170108,58sleep00-21swapper/019:05:150
1386421220,5sleep31424099cyclictest00:31:263
1423899307,22cyclictest0-21swapper/122:41:191
1423999299,19cyclictest0-21swapper/223:40:052
1423999295,23cyclictest0-21swapper/200:37:582
233032280,7sleep30-21swapper/300:05:183
1423899284,23cyclictest0-21swapper/121:24:001
1423999275,21cyclictest0-21swapper/222:44:122
1423899274,22cyclictest0-21swapper/122:32:431
1423899274,22cyclictest0-21swapper/121:51:041
14238992712,14cyclictest0-21swapper/122:06:571
14238992712,14cyclictest0-21swapper/122:06:571
1423999268,17cyclictest0-21swapper/221:46:442
1423999265,20cyclictest0-21swapper/223:46:412
1423999265,20cyclictest0-21swapper/222:58:592
1423999265,20cyclictest0-21swapper/221:19:542
1423999265,20cyclictest0-21swapper/200:00:082
1423999264,21cyclictest0-21swapper/223:52:292
1423999264,21cyclictest0-21swapper/222:25:202
14239992615,10cyclictest0-21swapper/222:45:582
1423899263,22cyclictest0-21swapper/123:45:161
14240992515,9cyclictest0-21swapper/323:59:163
1423999257,17cyclictest0-21swapper/222:19:222
1423999257,17cyclictest0-21swapper/221:43:512
1423999255,19cyclictest0-21swapper/223:37:492
1423999254,20cyclictest0-21swapper/222:06:302
1423999254,20cyclictest0-21swapper/222:06:302
1423999254,20cyclictest0-21swapper/200:08:122
1423999253,21cyclictest0-21swapper/223:57:512
1423999252,22cyclictest0-21swapper/222:22:572
1423999252,22cyclictest0-21swapper/200:13:262
14239992516,8cyclictest0-21swapper/223:20:402
14239992513,11cyclictest0-21swapper/223:00:542
1423899256,18cyclictest0-21swapper/100:10:131
1423899255,19cyclictest0-21swapper/121:43:371
14238992515,9cyclictest0-21swapper/123:05:041
14238992513,11cyclictest0-21swapper/123:41:081
14238992513,11cyclictest0-21swapper/122:56:171
14240992413,10cyclictest0-21swapper/322:15:583
1423999246,17cyclictest0-21swapper/200:33:172
1423999245,18cyclictest0-21swapper/222:01:302
1423999245,18cyclictest0-21swapper/222:01:302
1423999244,19cyclictest0-21swapper/222:13:412
1423999244,19cyclictest0-21swapper/200:23:442
1423999243,20cyclictest0-21swapper/223:26:192
14239992415,8cyclictest0-21swapper/223:31:042
14239992415,8cyclictest0-21swapper/223:17:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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