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2024-04-16 - 16:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Tue Apr 16, 2024 13:10:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5103
"cycles":100000000,5102
"load":"idle",5101
"condition":{5100
"clock":"2667"5098
"family":"x86",5097
"vendor":"Intel",5096
"processor":{5094
"dataset":"2024-01-08T03:37:02+0100"5092
"origin":"2024-01-08T00:43:21+0100",5091
"timestamps":{5090
"granularity":"microseconds"5088
3112:17:165086
48,12:16:465085
39,12:16:465084
23,12:16:465083
"maxima":[5082
012:16:465079
0,12:16:465078
0,12:16:465077
0,12:16:465076
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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