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2023-01-28 - 11:56

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Sat Jan 28, 2023 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18362199109,82sleep30-21swapper/319:07:233
17802178162,12sleep20-21swapper/219:06:462
20302172152,15sleep10-21swapper/119:09:331
18822171108,58sleep00-21swapper/019:07:560
83812930,1sleep00-21swapper/021:30:160
280652820,1sleep00-21swapper/000:30:230
280652820,1sleep00-21swapper/000:30:230
37152770,5sleep30-21swapper/300:06:113
173222730,1sleep00-21swapper/000:20:130
113712350,6sleep30-21swapper/323:10:123
2323993416,17cyclictest0-21swapper/100:10:011
58352320,6sleep30-21swapper/322:00:153
2324993124,6cyclictest0-21swapper/223:59:092
2323993023,6cyclictest0-21swapper/122:42:071
232499292,26cyclictest0-21swapper/223:50:242
2324992920,8cyclictest0-21swapper/223:12:322
2323992921,7cyclictest0-21swapper/123:57:191
2323992916,12cyclictest0-21swapper/100:29:291
232599285,22cyclictest0-21swapper/321:54:143
232499285,22cyclictest0-21swapper/222:13:422
232499283,24cyclictest0-21swapper/222:54:092
232499283,24cyclictest0-21swapper/221:10:212
232499282,25cyclictest0-21swapper/222:15:182
2324992818,9cyclictest0-21swapper/223:36:042
2324992816,11cyclictest0-21swapper/221:22:332
232399286,21cyclictest0-21swapper/123:43:491
232399283,24cyclictest0-21swapper/123:50:251
2323992818,9cyclictest0-21swapper/121:45:131
2323992816,11cyclictest0-21swapper/122:54:491
2323992816,11cyclictest0-21swapper/122:36:491
2323992816,11cyclictest0-21swapper/122:15:281
2323992816,11cyclictest0-21swapper/122:04:021
2323992816,11cyclictest0-21swapper/121:31:361
2323992816,11cyclictest0-21swapper/120:04:261
2323992816,11cyclictest0-21swapper/119:54:101
2323992816,11cyclictest0-21swapper/100:30:281
2323992816,11cyclictest0-21swapper/100:30:281
2323992816,11cyclictest0-21swapper/100:15:471
2323992816,11cyclictest0-21swapper/100:02:511
2323992815,12cyclictest0-21swapper/123:10:271
2323992815,12cyclictest0-21swapper/123:02:521
2323992814,13cyclictest0-21swapper/122:34:441
2323992813,6cyclictest0-21swapper/122:59:151
232499275,21cyclictest0-21swapper/221:18:002
232499274,22cyclictest0-21swapper/223:48:032
232499273,23cyclictest0-21swapper/223:00:212
232499273,23cyclictest0-21swapper/200:00:472
2324992716,10cyclictest0-21swapper/223:43:542
2324992716,10cyclictest0-21swapper/222:30:092
2324992716,10cyclictest0-21swapper/222:22:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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