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2023-06-02 - 01:12

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Thu Jun 01, 2023 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113022223104,114sleep20-21swapper/207:05:282
116472180105,70sleep30-21swapper/307:09:273
115482177158,15sleep10-21swapper/107:08:161
116542174105,65sleep00-21swapper/007:09:320
93962820,1sleep00-21swapper/012:01:530
11930993825,12cyclictest0-21swapper/210:21:342
11930993626,9cyclictest0-21swapper/211:44:522
11930993621,14cyclictest0-21swapper/212:14:222
11930993526,8cyclictest0-21swapper/211:37:052
11930993526,8cyclictest0-21swapper/210:40:252
11930993526,8cyclictest0-21swapper/210:08:552
11930993526,8cyclictest0-21swapper/209:57:332
11930993525,9cyclictest0-21swapper/212:21:282
11930993525,9cyclictest0-21swapper/212:19:532
11930993525,9cyclictest0-21swapper/212:04:112
11930993525,9cyclictest0-21swapper/211:54:262
11930993525,9cyclictest0-21swapper/211:47:132
11930993525,9cyclictest0-21swapper/211:05:272
11930993525,9cyclictest0-21swapper/210:57:332
11930993525,9cyclictest0-21swapper/210:10:592
11930993525,9cyclictest0-21swapper/209:44:552
11930993521,13cyclictest0-21swapper/209:37:272
11930993521,13cyclictest0-21swapper/209:12:202
11930993520,14cyclictest0-21swapper/208:34:032
11930993519,15cyclictest0-21swapper/210:18:322
11930993427,6cyclictest0-21swapper/211:28:262
11930993426,7cyclictest0-21swapper/210:03:412
11930993425,8cyclictest0-21swapper/212:31:232
11930993425,8cyclictest0-21swapper/212:07:202
11930993425,8cyclictest0-21swapper/211:56:142
11930993425,8cyclictest0-21swapper/211:34:082
11930993425,8cyclictest0-21swapper/211:21:092
11930993425,8cyclictest0-21swapper/211:15:192
11930993425,8cyclictest0-21swapper/210:45:542
11930993425,8cyclictest0-21swapper/210:33:572
11930993425,8cyclictest0-21swapper/210:26:152
11930993425,8cyclictest0-21swapper/209:50:422
11930993425,8cyclictest0-21swapper/209:49:412
11930993425,8cyclictest0-21swapper/209:32:382
11930993425,8cyclictest0-21swapper/209:28:132
11930993425,8cyclictest0-21swapper/209:20:032
11930993425,8cyclictest0-21swapper/209:17:442
11930993424,9cyclictest0-21swapper/211:14:212
11930993424,9cyclictest0-21swapper/208:00:212
11930993423,8cyclictest0-21swapper/208:12:052
11930993423,10cyclictest0-21swapper/210:50:342
11930993423,10cyclictest0-21swapper/210:50:332
11930993422,11cyclictest0-21swapper/210:38:142
11937993314,18cyclictest39652sleep308:08:133
11937993314,18cyclictest258382sleep307:41:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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