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2022-06-29 - 15:39

x86 Intel Core i5-750 @2667 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #8, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Wed Jun 29, 2022 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117262205105,95sleep30-21swapper/307:09:333
115192183165,13sleep20-21swapper/207:07:152
115612179160,12sleep10-21swapper/107:07:421
116112174105,65sleep00-21swapper/007:08:180
1127921130,2sleep20-21swapper/210:03:232
258972850,5sleep30-21swapper/311:35:003
1201399299,19cyclictest0-21swapper/210:40:192
1201399298,20cyclictest0-21swapper/210:28:412
1201399287,20cyclictest0-21swapper/212:28:182
1201399287,20cyclictest0-21swapper/211:37:402
1201399287,20cyclictest0-21swapper/210:20:072
1201399285,22cyclictest0-21swapper/209:40:052
1201399284,23cyclictest0-21swapper/211:20:192
12013992815,12cyclictest0-21swapper/212:20:232
12013992815,11cyclictest8032-21ssh11:14:252
12013992815,11cyclictest5473-21ssh10:34:122
12013992815,11cyclictest30884-21runrttasks11:02:572
1201299284,23cyclictest0-21swapper/111:23:361
1201399279,17cyclictest0-21swapper/212:12:562
1201399278,18cyclictest0-21swapper/212:35:342
1201399278,18cyclictest0-21swapper/211:47:302
1201399278,18cyclictest0-21swapper/211:40:182
1201399278,18cyclictest0-21swapper/211:28:372
1201399275,21cyclictest0-21swapper/210:47:452
1201399275,21cyclictest0-21swapper/209:49:302
1201399274,22cyclictest0-21swapper/209:24:242
12013992715,11cyclictest3053-21ssh09:54:302
12013992715,11cyclictest28873-21diskmemload09:59:042
12013992715,11cyclictest21468-21ssh09:37:532
12013992715,10cyclictest3389-21runrttasks10:06:462
1201299277,19cyclictest0-21swapper/109:35:301
1201399268,18cyclictest0-21swapper/210:12:232
1201399268,18cyclictest0-21swapper/210:12:232
1201399268,17cyclictest0-21swapper/211:58:022
1201399268,17cyclictest0-21swapper/209:29:072
1201399268,17cyclictest0-21swapper/209:18:052
1201399268,17cyclictest0-21swapper/209:11:002
1201399265,20cyclictest0-21swapper/211:06:072
1201399263,22cyclictest0-21swapper/210:56:242
12013992615,10cyclictest308992sleep207:55:132
12013992615,10cyclictest2650-21automount08:58:092
12013992615,10cyclictest2650-21automount08:00:452
12013992615,10cyclictest177852sleep209:34:042
12013992614,11cyclictest2940-21qpidd11:50:332
12013992614,10cyclictest21176-21ssh10:51:082
12013992613,12cyclictest2940-21qpidd12:16:022
1201299268,17cyclictest0-21swapper/112:13:361
1201299267,18cyclictest0-21swapper/112:04:181
1201299267,18cyclictest0-21swapper/110:07:541
1201299267,18cyclictest0-21swapper/109:28:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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