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2021-10-16 - 13:22

Intel(R) Core(TM) i5-8365UE CPU @ 1.60GHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #8, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack8slot4.osadl.org (updated Mon Apr 15, 2019 12:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243242754713,28sleep30-21swapper/307:08:553
340480566479,56exc_00000111_CO0-21swapper/007:06:040
242812481432,36sleep10-21swapper/107:08:201
242252441393,34sleep20-21swapper/207:07:412
2445999326,2cyclictest9989-21ssh11:30:240
2445999283,16cyclictest2544-21nscd09:31:060
2445999270,25cyclictest0-21swapper/009:55:120
2446199261,6cyclictest0-21swapper/210:58:112
2446199261,10cyclictest0-21swapper/210:32:542
2445999265,18cyclictest0-21swapper/010:06:150
2445999265,18cyclictest0-21swapper/010:00:100
2445999241,17cyclictest0-21swapper/011:20:070
2446199231,12cyclictest0-21swapper/212:25:532
2445999235,11cyclictest0-21swapper/009:20:120
2445999233,12cyclictest28287-21diskmemload12:15:000
2445999231,7cyclictest0-21swapper/010:21:040
24459992313,4cyclictest0-21swapper/008:21:130
2445999231,17cyclictest0-21swapper/011:12:410
2445999230,21cyclictest0-21swapper/012:31:380
2445999230,21cyclictest0-21swapper/012:18:210
2445999230,21cyclictest0-21swapper/012:04:520
2445999230,21cyclictest0-21swapper/009:44:020
2445999230,21cyclictest0-21swapper/009:15:080
2446299221,5cyclictest0-21swapper/310:24:183
2446299221,12cyclictest0-21swapper/312:25:033
2446199222,11cyclictest0-21swapper/211:02:332
2446199221,11cyclictest0-21swapper/212:34:532
2445999226,8cyclictest0-21swapper/010:00:420
2445999224,13cyclictest0-21swapper/010:16:560
2445999221,15cyclictest0-21swapper/011:08:290
24459992210,6cyclictest0-21swapper/010:27:330
2445999220,20cyclictest0-21swapper/012:36:050
2445999220,20cyclictest0-21swapper/010:49:210
2445999220,20cyclictest0-21swapper/010:44:510
2445999220,20cyclictest0-21swapper/009:22:450
2446299217,5cyclictest31911-21ssh09:14:263
2446299211,13cyclictest0-21swapper/311:17:043
2446299211,11cyclictest0-21swapper/311:54:403
24462992110,3cyclictest27724-21dmmpower09:50:063
2446199212,11cyclictest0-21swapper/212:24:282
2446199212,11cyclictest0-21swapper/208:12:292
2446199211,10cyclictest0-21swapper/211:07:402
2446199211,10cyclictest0-21swapper/210:43:482
2446199211,10cyclictest0-21swapper/209:34:492
2446199210,11cyclictest0-21swapper/210:49:432
2446099211,12cyclictest0-21swapper/112:20:371
2445999219,10cyclictest0-21swapper/011:59:060
2445999217,7cyclictest0-21swapper/010:52:410
2445999215,8cyclictest0-21swapper/011:03:520
2445999211,6cyclictest0-21swapper/011:53:230
2445999211,6cyclictest0-21swapper/010:55:230
2445999211,4cyclictest0-21swapper/011:44:370
2445999211,3cyclictest323-21ssh10:37:340
2445999211,14cyclictest175050irq/108-eth0-tx09:45:190
2445999211,14cyclictest0-21swapper/011:26:520
2445999211,14cyclictest0-21swapper/009:37:460
2445999210,19cyclictest0-21swapper/012:27:400
2445999210,19cyclictest0-21swapper/012:22:500
2445999210,19cyclictest0-21swapper/012:06:590
2446299203,11cyclictest175050irq/108-eth0-tx10:07:353
2446299201,9cyclictest0-21swapper/310:31:043
2446299201,3cyclictest0-21swapper/310:57:453
2446299201,12cyclictest0-21swapper/312:30:413
2446299201,12cyclictest0-21swapper/311:33:523
2446299201,12cyclictest0-21swapper/311:00:453
2446299201,11cyclictest0-21swapper/310:39:263
2446299201,11cyclictest0-21swapper/310:20:003
2446299201,11cyclictest0-21swapper/309:26:393
2446299201,11cyclictest0-21swapper/307:49:273
2446299201,10cyclictest0-21swapper/311:06:493
2446299201,10cyclictest0-21swapper/310:27:033
2446299201,10cyclictest0-21swapper/309:38:483
2446299200,12cyclictest20841-21ssh12:25:523
2446199202,2cyclictest0-21swapper/212:18:242
2446199201,9cyclictest0-21swapper/209:25:132
2446199201,11cyclictest0-21swapper/210:24:442
2446199201,11cyclictest0-21swapper/207:21:222
2446199201,10cyclictest0-21swapper/211:49:322
2446199201,10cyclictest0-21swapper/211:10:312
2446199201,10cyclictest0-21swapper/210:38:382
2446199201,10cyclictest0-21swapper/209:38:132
2446199201,10cyclictest0-21swapper/207:29:162
2446199200,3cyclictest0-21swapper/210:05:362
2446199200,10cyclictest0-21swapper/210:28:212
2446099204,10cyclictest174850irq/106-eth0-rx12:38:571
2446099201,10cyclictest0-21swapper/109:51:101
2445999208,6cyclictest0-21swapper/011:40:010
2445999201,6cyclictest0-21swapper/009:27:460
24459992012,2cyclictest175050irq/108-eth0-tx08:45:100
2445999201,17cyclictest0-21swapper/010:12:120
2445999200,6cyclictest0-21swapper/007:19:500
2445999200,18cyclictest227522sleep011:47:140
2445999200,18cyclictest0-21swapper/010:33:280
2446299191,9cyclictest0-21swapper/310:45:473
2446299191,12cyclictest174850irq/106-eth0-rx12:35:133
2446299191,11cyclictest0-21swapper/309:21:453
2446299191,11cyclictest0-21swapper/309:16:013
2446299191,10cyclictest0-21swapper/311:56:103
2446299191,10cyclictest0-21swapper/310:50:343
2446299191,10cyclictest0-21swapper/310:41:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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